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AMD 3rd Gen EPYC Milan Review

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Re: AMD 3rd Gen EPYC Milan Review

#41

Post by dragontamer »

masklinn wrote: post #30
dragontamer wrote: post #24

Earlier quoted context omitted.

How is it suspicious? 256MB L3 (or really, 8 x 32MBs L3) and 24-cores suggests the bottom-of-the-barrel 3 cores active per 8-core CCX. 8x CCX with 3-cores. The yields on those chips must be outstanding: its like 62.5% of the cores could have critical errors and they can still sell it at that price. EDIT: My numbers were wrong at first. Fixed. Zen3 is double-sized CCX (32MBs / CCX instead of 16MBs/CCX) --------- In co…

> In contrast, the 28-core 7453 is $1,570. Which is cheaper than the 24c 7443 and 7413 but not the 16c 7343 and 7313. And it only has half the L3 compared to its siblings (1/4th compared to the 7543 top end), a lower turbo than every other processor in the range (whether lower or higher core counts), well as an unimpressive base frequency, and a fairly high TDP by comparison (as high as the 7543). The 74F3 has no suc…

> Which is cheaper than the 24c 7443 and 7413 but not the 16c 7343 and 7313.

28-cores for $1570 seems to be the "cheapest per core" in the entire lineup.

It all comes down to whether you want those cores actually communicating over L3 cache, or not. Do you want 7-cores per L3 cache, or do you prefer 4-cores per L3 cache?

4-cores per L3 cache benefits from having more overall cache per core. But more-cores per L3 cache means that more of your threads can tightly-communicate cheaply, and effectively.

---------

More L3 cache probably benefits from cloud-deployments, Virtual Desktops, and similar (since those cores aren't communicating as much).

More cores per L3 cache benefits from more tightly integrated multicore applications.

EDIT: Also note that "more cores" means more L1 and L2 cache, which is arguably more important in compute-heavy situations. L3 cache size is great of course, but many applications are L1 / L2 constrained and will prefer more cores instead. 24c 7443 with 2x32MB L3 is probably a better chess-engine than 16c 7343 4x32MB L3.

Re: AMD 3rd Gen EPYC Milan Review

#43

Post by dragontamer »

zhdc1 wrote: post #42

It looks like Zen 2 processors about about to become even more of a bargain than they already are. I'll take a 7702P at $2-3K over a 7713P at $5K ten times out of ten.

Considering both are made from the 7nm TSMC process, AMD probably aren't going to make any more Zen2 processors at this point.

I think you're right: that buying a generation old or so can offer gross cost savings. But that's only true for the time-period where those chips are available.

Re: AMD 3rd Gen EPYC Milan Review

#44

Post by dragontamer »

cm2187 wrote: post #37
rbanffy wrote: post #8

There must be a typo on the 74F3 price. US$2900 for it is a steal.

I am building a single socket server right now, I can't really justify more than twice the price of a 7443P for a marginally higher base clock and twice the cache. Does the cache makes that much of a difference? I thought these are already very large caches vs lots of Intel CPUs.

Hmm, with AMD Threadripper, you're already looking at TLB issues at these L3 sizes. So if you actually want to take advantage of lots of L3, you need either many cores, or hugepages.

Case in point: AMD Zen2 has 2048 TLB entries (L2), under a default (in Linux and Windows) of 4kB per TLB entry. That's 8MBs of TLB before your processor starts to page-walk.

Emphasis: Your application will pagewalk when the data still fits in L3 cache.

------------

I'm looking at some of this lineup with 3-cores per CCX (32MBs L3 cache), which means under default 4kB pages, those cores will always require a pagewalk to just read/write its 32MBs L3 cache effectively.

With that being said: 2048 TLB entries for Zen2 processors. Maybe AMD has increased the TLB entries for Zen3. Either way, you probably should start looking at hugepage configuration settings...

These L3 cache sizes are absurd, to the point where its kind of unwieldy. I mean, with enough configuration / programming, you can really make these things fly. But its not exactly plug-and-play.

Re: AMD 3rd Gen EPYC Milan Review

#45

Post by kllrnohj »

unicornfinder wrote: post #34
epmaybe wrote: post #9

Earlier quoted context omitted.

Performance per watt is better on amd right now, at least last I heard.

Performance per watt is better but unfortunately the idle power consumption is fairly high.

Epyc's idle power consumption is fairly high but Ryzen's isn't. The more workstation-focused Threadripper & Threadripper Pro is also still significantly better than Epyc here.

Re: AMD 3rd Gen EPYC Milan Review

#46

Post by uluyol »

totalZero wrote: post #29
xirbeosbwo1234 wrote: post #25

Earlier quoted context omitted.

First off, it's not a direct comparison. The Epyc has one L3 cache per chiplet. This means that latency is not uniform across the entire L3 cache. This was a serious concern on the first generation of Epyc, where accessing L3 could take anywhere from zero to three hops across an internal network. AMD has greatly improved the problem on the more recent generations by switching to a star topology with more predictable…

What is the likelihood that mixed-process chiplets become the state of the art?

Intel already said they would use chiplets [1] and TSMC has been talking about the various packaging technologies being developed [2].

[1] https://www.anandtech.com/show/16021/intel-moving-to-chiplet...

[2] https://www.anandtech.com/show/16051/3dfabric-the-home-for-t...

Re: AMD 3rd Gen EPYC Milan Review

#47

Post by Macha »

totalZero wrote: post #29
xirbeosbwo1234 wrote: post #25

Earlier quoted context omitted.

First off, it's not a direct comparison. The Epyc has one L3 cache per chiplet. This means that latency is not uniform across the entire L3 cache. This was a serious concern on the first generation of Epyc, where accessing L3 could take anywhere from zero to three hops across an internal network. AMD has greatly improved the problem on the more recent generations by switching to a star topology with more predictable…

What is the likelihood that mixed-process chiplets become the state of the art?

Aren't they already for big (desktop/workstation/server) chips? I'd say Zen3 is the state of the art in that market and that uses a mixed process. The IO dies are global foundries 12nm for AMD.

The mobile market cares more about efficiency than easily scaling up to much bigger chips, so the M1 and other ARM chips are probably going to ignore this without much consequence for smaller chips.

Intel still tops sales because of non-perf related reasons like refresh cycles, distrust of AMD from last time they fell apart in the server space, producing chips in sufficient quantities unlike the entire rest of the industry fighting over TSMC's capacity, etc.

Re: AMD 3rd Gen EPYC Milan Review

#48

Post by rbanffy »

dragontamer wrote: post #13
rbanffy wrote: post #5

Why so little L3 cache on the competition?

EPYC is a split L3 cache. Any particular core only benefits from 32MBs of L3, the 33rd MB is "on another chip". (EDIT: Zen2 was 16MBs, Zen3 is 32MBs. Fixed numbers for Zen3) As such, AMD can make absolutely huge amounts of L3 cache (well, many parallel L3 clusters), while other CPU designers need to figure out how to combine the L3 so that a single core can benefit it from it all.

What AMD does is not magic and is not beyond what others can do. My question is why they chose to have just 32MB for up to 80 cores when AMD can choose to have 32MB per 8-core chiplet.

As a comparison, an IBM z15 mainframe CPU has 10 cores and 256MB per socket.

Re: AMD 3rd Gen EPYC Milan Review

#49

Post by blinkingled » 

   INVLPGB New instruction to use instead of inter-core 
   unterrupts to broadcast page invalidates, requires 
   OS/hypervisor support
   
   VAES / VPCLMULQDQ AVX2 Instructions for 
   encryption/decryption acceleration
   
   SEV-ES Limits the interruptions a malicious hypervisor may 
   inject into a VM/instance

   Memory Protection Keys Application control for access- 
   disable and write-disable settings without TLB management
  
   Process Context ID (PCID) Process tags in TLB to reduce 
   flush requirements
Interruptions (Instructions) and Unterrupts (Interrupts) aside (the article obviously was pushed out as fast as AT could lol) - these additions seem like they would help with performance when it comes to mitigations of all the speculation vulnerabilities in an hypervisor env?

Re: AMD 3rd Gen EPYC Milan Review

#50

Post by IanCutress »

dragontamer wrote: post #43
zhdc1 wrote: post #42

It looks like Zen 2 processors about about to become even more of a bargain than they already are. I'll take a 7702P at $2-3K over a 7713P at $5K ten times out of ten.

Considering both are made from the 7nm TSMC process, AMD probably aren't going to make any more Zen2 processors at this point. I think you're right: that buying a generation old or so can offer gross cost savings. But that's only true for the time-period where those chips are available.

AMD is going to keep Zen 2 EPYC sales going for a good while yet. Both families will co-exist in the market.
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