Forth SoC Written in VHDL • Hacker News Board

Re: Forth SoC Written in VHDL

#11

Post by howerj » Thu, Feb 18, 2021, 10:25 PM UTC

analognoise wrote: post #10

I've been considering attempting something like this with Verilator output which is mixed into a GUI produced by QT. This is truly awesome. I can't wait to play with it!

I almost got VHDL STDIN/STDOUT UART H2 core working, which would have allowed you to interact at run time with the VHDL simulation, but I do not think it is possible to do without using non-standard extensions, which is a shame. The attempt is still in "tb.vhd" and can be turned on by modifying "tb.cfg". I was quite impressed that I managed to get a VHDL program that could process a text file at run time so I did not have to keep compiling it.

Re: Forth SoC Written in VHDL

#12

Post by LargoLasskhyfv » Fri, Feb 19, 2021, 6:17 AM UTC

digiou wrote: post #8

Silly idea, is there any Lisp SoC, like the famed Lisp machines?

Build one. Like this: https://en.wikipedia.org/wiki/SECD_machine

Or maybe use that SoC with its FORTH as microcode to implement SECD on top of it.

Or look into https://github.com/kanaka/mal & https://en.wikipedia.org/wiki/POP-11 for matching and mixing.

Re: Forth SoC Written in VHDL

#13

Post by jecel » Fri, Feb 19, 2021, 6:14 PM UTC

digiou wrote: post #8

Silly idea, is there any Lisp SoC, like the famed Lisp machines?

https://github.com/lisper/cpus-caddr