Forth SoC Written in VHDL
github.com
Forth SoC Written in VHDL
1–10 of 13 posts
Re: Forth SoC Written in VHDL
#2Can this run on a VDHL simulator?
Re: Forth SoC Written in VHDL
#3Can this run on a VDHL simulator?
Yes, although you will only get waveforms as an output. There is a fully interactive GUI simulator (type "make gui-run" to build it and run it), and a command line simulator as well (just type "make run").
Re: Forth SoC Written in VHDL
#4I wonder if this would fit in a Lattice ICE40 FPGA so that Xilinx ISE could be avoided (very buggy) and open source tools like Yosys could be used instead.
Re: Forth SoC Written in VHDL
#5Looks interesting, it is known that J1 is very tiny, how many can fit in the Spartan-6 XC6LX16 mentioned, do you have plan of create a multi-core system with this?
Re: Forth SoC Written in VHDL
#6I wonder if this would fit in a Lattice ICE40 FPGA so that Xilinx ISE could be avoided (very buggy) and open source tools like Yosys could be used instead.
It will fit in an 8K easily. There was a version of the j1 (that this was based on) running on an IceStick with a 1K part.
https://www.excamera.com/sphinx/article-j1a-swapforth.html
Re: Forth SoC Written in VHDL
#7I wonder if this would fit in a Lattice ICE40 FPGA so that Xilinx ISE could be avoided (very buggy) and open source tools like Yosys could be used instead.
It will fit in an 8K easily. There was a version of the j1 (that this was based on) running on an IceStick with a 1K part. https://www.excamera.com/sphinx/article-j1a-swapforth.html
It should fit, as you said, but the last time I tried it the VHDL front-end for Yosys was not up to it. That might have changed as it was a few years ago.
Re: Forth SoC Written in VHDL
#8Silly idea, is there any Lisp SoC, like the famed Lisp machines?
Re: Forth SoC Written in VHDL
#9Earlier quoted context omitted.
It will fit in an 8K easily. There was a version of the j1 (that this was based on) running on an IceStick with a 1K part. https://www.excamera.com/sphinx/article-j1a-swapforth.html
It should fit, as you said, but the last time I tried it the VHDL front-end for Yosys was not up to it. That might have changed as it was a few years ago.
It is (I think) much better now - it is ghdl as a plugin synthesising to yosys IR. The nightlies from https://github.com/YosysHQ/fpga-toolchain have it all ready to go.
Re: Forth SoC Written in VHDL
#10I've been considering attempting something like this with Verilator output which is mixed into a GUI produced by QT.
This is truly awesome. I can't wait to play with it!