Live data from Hacker News

FPGA NTP Server

research.wand.net.nz

11–20 of 70 posts

Re: FPGA NTP Server

#11
post #10
post #8

Earlier quoted context omitted.

PTP seems like a telco/enterprise thing; hackers don't care about it.

I personally enjoyed the challenge of setting up PTP at home. Why would a hacker scoff at nanosecond-level timekeeping —- isn’t the entire internet a “telco/enterprise” thing?

did you write about your experience? I am interested in this but have very limited knowledge about it at this point.

Re: FPGA NTP Server

#12
post #9
post #7

Earlier quoted context omitted.

Less than $200. The board there is overkill -- if you really want something with a Zynq including an Arm Cortex A9 that can run Linux, the Arty Z7 from Digilent is another Zynq board that's essentially a one-stop shop for this: https://store.digilentinc.com/arty-z7-zynq-7000-soc-developm... However, for something as simple as an NTP server you could easily get away with an Arty A7: https://store.digilentinc.com/arty-…

thank you for providing all this info! as someone who doesn't know much about fgpa boards, what does it mean when you write "From there you can instantiate either Xilinx's Microblaze MCU"? Also, one thing that is confusing to me is that the source code that is linked on this page is a .h and .c file, is the fgpa on these zynq boards programmable with C code?

[deleted]

Re: FPGA NTP Server

#13
post #10
post #8

Earlier quoted context omitted.

PTP seems like a telco/enterprise thing; hackers don't care about it.

I personally enjoyed the challenge of setting up PTP at home. Why would a hacker scoff at nanosecond-level timekeeping —- isn’t the entire internet a “telco/enterprise” thing?

To do PTP "right" requires every switch to support it and a NIC with hardware timestamps. Also, I've seen claims that PTP is no more precise than a good implementation of NTP.

Re: FPGA NTP Server

#14
post #13
post #10

Earlier quoted context omitted.

I personally enjoyed the challenge of setting up PTP at home. Why would a hacker scoff at nanosecond-level timekeeping —- isn’t the entire internet a “telco/enterprise” thing?

To do PTP "right" requires every switch to support it and a NIC with hardware timestamps. Also, I've seen claims that PTP is no more precise than a good implementation of NTP.

ptp is If you look at the white rabbit FPGA PTP updates, its in the ns range.

Any kind of GPS + most intel nics will get you PTP with an accurate clock. If you didn't need to sync too many devices you could use a single system with a bunch of nics as your "switch".

Re: FPGA NTP Server

#15
post #9
post #7

Earlier quoted context omitted.

Less than $200. The board there is overkill -- if you really want something with a Zynq including an Arm Cortex A9 that can run Linux, the Arty Z7 from Digilent is another Zynq board that's essentially a one-stop shop for this: https://store.digilentinc.com/arty-z7-zynq-7000-soc-developm... However, for something as simple as an NTP server you could easily get away with an Arty A7: https://store.digilentinc.com/arty-…

thank you for providing all this info! as someone who doesn't know much about fgpa boards, what does it mean when you write "From there you can instantiate either Xilinx's Microblaze MCU"? Also, one thing that is confusing to me is that the source code that is linked on this page is a .h and .c file, is the fgpa on these zynq boards programmable with C code?

They mean putting a “soft” CPU core on the FPGA.

“Soft” means the CPU is added to your overall design as a block and is compiled along with your design to the FPGA bitstream. This way, the CPU ends up being implemented (instantiated) on the FPGA. This approach eats into your overall FPGA resource budget and leads to lower CPU performance due to the FPGA overhead.

The alternative to a soft core is a “hard” CPU core, which simply means that the CPU is included in a separate area of silicon (usually on the same die). The Zynq 7000 is a good example.

Re: FPGA NTP Server

#16
post #13

Earlier quoted context omitted.

To do PTP "right" requires every switch to support it and a NIC with hardware timestamps. Also, I've seen claims that PTP is no more precise than a good implementation of NTP.

ptp is If you look at the white rabbit FPGA PTP updates, its in the ns range. Any kind of GPS + most intel nics will get you PTP with an accurate clock. If you didn't need to sync too many devices you could use a single system with a bunch of nics as your "switch".

This post didn’t sound right to me, but I realized that my raspi4 GPS NTP server has been running ntp and not chrony. Chrony is better at modeling non deterministic timing behavior, so I swapped to that.

It’s been ten minutes now and chronyc tracking has been marching the offset down. It’s sub 1 us at this point.

  System time     : 0.000000123 seconds fast of NTP time
  Last offset     : +0.000000366 seconds
How to get this precise time out of a non deterministic OS? Beats me. Once I figure that out I can finish my clock project.

My best lead is to step through the different python timing and scheduler implementations and see which has the lowest jitter relative to the PPS on an oscilloscope.

Re: FPGA NTP Server

#17
post #10
post #8

Earlier quoted context omitted.

PTP seems like a telco/enterprise thing; hackers don't care about it.

I personally enjoyed the challenge of setting up PTP at home. Why would a hacker scoff at nanosecond-level timekeeping —- isn’t the entire internet a “telco/enterprise” thing?

Many many computers on the internet have a RTC with second resolution and timer tick resolution in the microseconds. Reference time resolution that's that much higher than your timer tick period is useless.

Re: FPGA NTP Server

#19

Earlier quoted context omitted.

ptp is If you look at the white rabbit FPGA PTP updates, its in the ns range. Any kind of GPS + most intel nics will get you PTP with an accurate clock. If you didn't need to sync too many devices you could use a single system with a bunch of nics as your "switch".

This post didn’t sound right to me, but I realized that my raspi4 GPS NTP server has been running ntp and not chrony. Chrony is better at modeling non deterministic timing behavior, so I swapped to that. It’s been ten minutes now and chronyc tracking has been marching the offset down. It’s sub 1 us at this point. System time : 0.000000123 seconds fast of NTP time Last offset : +0.000000366 seconds How to get this pre…

I've always had a lot of trouble getting low jitter with python. C is much better.

Re: FPGA NTP Server

#20
post #13

Earlier quoted context omitted.

To do PTP "right" requires every switch to support it and a NIC with hardware timestamps. Also, I've seen claims that PTP is no more precise than a good implementation of NTP.

ptp is If you look at the white rabbit FPGA PTP updates, its in the ns range. Any kind of GPS + most intel nics will get you PTP with an accurate clock. If you didn't need to sync too many devices you could use a single system with a bunch of nics as your "switch".

NTP gets worse if you sync more than two devices across a broader network with other switched traffic, more into low 100s of µs. PTP does not degrade similarly and yes, most of PHYs made since middle of the last decade support it.
Post reply on HN