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RAM is the new disk – and how to measure its performance (2015)

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Re: RAM is the new disk – and how to measure its performance (2015)

#61
post #50

Earlier quoted context omitted.

There are NICs that more or less run BPF for exactly those reasons.

Give me SQLite running directly on an nvme card.

I've actually heard rumors of SSD controller firmware that uses SQLite internally.

Not quite what you're asking for, for sure.

Re: RAM is the new disk – and how to measure its performance (2015)

#62
post #50

Earlier quoted context omitted.

Give me SQLite running directly on an nvme card.

I've actually heard rumors of SSD controller firmware that uses SQLite internally. Not quite what you're asking for, for sure.

To track cell health? Or to queue writes? Or both?

Re: RAM is the new disk – and how to measure its performance (2015)

#63

I think how DMA operates needs another serious look. Right now we have to fetch everything into the CPU before we can make decisions. What if we had asynchronous HW embedded within the memory that could be given a small (safe) executable program to process the memory in-place rather than evaluating it on the CPU. In other words, a linked list would be much faster and simpler to traverse. A lot of the software archite…

There are some memories supporting basic in-memory operations. For example: https://mosys.com/products/blazar-family/be3rmw-bandwidth-en... . This supports operations like read-modify-write within the memory device itself. (I have no affiliation with this company.) The barrier to adoption of this is not technical, it's economic. Memory industry has focused on making the highest capacity and lowest cost/bit products.…

Sounds like http://iram.cs.berkeley.edu/ and the meanwhile flopped Micron Automata Processor (Micron AP).

Re: RAM is the new disk – and how to measure its performance (2015)

#64
post #36

Earlier quoted context omitted.

why is that? we need the CPU to handle page fault interrupts, in order to populate the RAM. But assuming the page is already in RAM, there's no reason any of the memory accesses actually need to go through the CPU. (hardware can already raise interrupts; if the MMU can raise a page fault indicator, then you might be able to bypass CPU entirely until a new page needs to be loaded) moreover, if we have support for mmap…

Pointers are virtual addresses but memory is accessed physically. All of the means of translating virtual to physical are in the CPU. If you are proposing throwing out virtual addressing, I imagine you won't get a lot of support for that idea.

I think the point was more like the following situation.

You have a linked list. Each memory location, since it’s user-space, stores the virtual address to the next location. How do you offload a program to process this “in situ”? You’d need to translate these to physical addresses. Parent is 100% correct about the challenge this poses.

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