Earlier quoted context omitted.
Speaking of Itanium, if the x86 dam has truly burst, I'd much rather see something more like the Itanium than RISC-V. Something new. It's a shame the Mill is so secretive, actually, they're design is rather nice.
Nah I think the Itanic concept is dead in the water VLIW works (especially in the way it was done in Itanium - IIRC) when either your workload is too predictable or maybe if your compiler manages to be one order of magnitude smarter than it is today (even with llvm, etc) It seems even M1 prefers to reorder scalar operations than work with SIMD ops in some cases (this is one of its processors)
If you look at uops executed per port benchmarks you can see that CPUs are far from all seeing eyes.