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Debian 11 “bullseye” freeze started

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Re: Debian 11 “bullseye” freeze started

#91
post #79

Earlier quoted context omitted.

As someone who doesn't use Debian as my only (or even main) OS, but does manage a few Debian servers, I completely disagree on memorable. I can never remember the order of code names and whenever I read something like "stretch or later" I always have to Google to find out if the servers I have qualify or not. Other than that, I have zero complaints about Debian

> I can never remember the order of code names... Me neither, don't worry about it :) > I read something like "stretch or later"... Well, they're really irresponsible if they're writing like that. All of the places I've seen, downloaded debs either write Debian 9+ or Debian 9+ (Stretch and later) or any similar fashion. I didn't encounter any Debian $codename only compatibility notes. I also don't write $codename onl…

> All of the places I've seen, downloaded debs either write Debian 9+ or Debian 9+

Just a couple of recent examples I stumbled upon:

https://www.armbian.com/nanopi-r2s/#kernels-archive-all

https://louwrentius.com/configuring-scst-iscsi-target-on-deb...

Sure a bit of searching lets me figure out what's what but...

Re: Debian 11 “bullseye” freeze started

#92
post #70
post #34

Earlier quoted context omitted.

MIPS has no SMP memory model. One could be cribbed from POWER or ARM, or even x86, but it is a paste-up.

Well, SGI used to make those huge shared memory NUMA machines based on MIPS (then they switched to IA-64, after that x86-64, and then they got bought by HPE). But yes, I guess that's far enough back in time that they didn't have any formal model for the behavior. I guess they had some kind of prose specification, and then they just winged it.

My recollection (from discussion with an engineer on that project) was that they were using Itanium there. They used Itanium in preference to amd64 because amd64 had one fewer address pin than they memory they wanted to put on needed.

Re: Debian 11 “bullseye” freeze started

#93
post #92
post #70

Earlier quoted context omitted.

Well, SGI used to make those huge shared memory NUMA machines based on MIPS (then they switched to IA-64, after that x86-64, and then they got bought by HPE). But yes, I guess that's far enough back in time that they didn't have any formal model for the behavior. I guess they had some kind of prose specification, and then they just winged it.

My recollection (from discussion with an engineer on that project) was that they were using Itanium there. They used Itanium in preference to amd64 because amd64 had one fewer address pin than they memory they wanted to put on needed.

They sold multiple generations of these huge NUMA machines. First were the MIPS-based Origin 2000 and 3000 (https://en.wikipedia.org/wiki/SGI_Origin_2000 and https://en.wikipedia.org/wiki/SGI_Origin_3000_and_Onyx_3000#... ) supporting up to 512 CPU's running Irix, then came the Itanium-based Altix (https://en.wikipedia.org/wiki/Altix ) with up to 4096 cores running Linux, then finally the x86-64 based Altix UV supporting up to 2048 cores, also running Linux.
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