Earlier quoted context omitted.
Something I've seen no one else mentioning: Apple's low-spec tier is $1000, not $70.
It's $699, for a complete device, not a part of one.
What's the screen resolution on that $699 "complete device"?
Memory access on the Apple M1 processor
231–240 of 278 posts
Re: Memory access on the Apple M1 processor
#232Interesting article.
Re: Memory access on the Apple M1 processor
#233Earlier quoted context omitted.
Here's the M1: https://www.anandtech.com/show/16252/mac-mini-apple-m1-teste... Scroll down to the latency vs size map and look at the R per RV prange. That gets you 30ns or so. Similar for AMD's latest/greatest the Ryzen 9 5950X: https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-di... The same R per RV prange is in the 60ns range.
Could this be coming from the page size being 4x as large for Apple Silicon versus x86? I don't fully understand the benchmark, but it appears to be accessing a variety of pages from the same first level TLB lookup? It's been a long time since I dealt with this stuff (wanted to get 1GB huge pages in Linux for some huge huge hash tables), so maybe I'm misunderstanding.
Cachelines, page sizes, and size of the TLB all play a role. But with tinkering you can see those effects yourself and I played with 1, 2, 4, 8, 16, and 32 "pages" which I assumed were 4KB each and didn't see much difference. Measured latencies do increase slowly, but you expect that as the TLB becomes progressively more of a bottleneck.
If you use a 1GB array and see full random with much higher latency than a sliding window then you can be pretty sure that the page size is much less than 1GB.
Getting the cacheline off by a factor of 2 does make a small difference since you get occasional cache hits instead of zero, but as long as the array tested is several times larger than cache the impact is small.
But all in all the M1 has excellent memory bandwidth, excellent latency, and shows significantly better throughput on random workloads as you use more cores. Normal PC desktops have 2 memory channels (even the higher end i7/i9/ryzen7/ryzen9), only the $$$$ workstation chips like threadripper and some of the $$$$ Intel's have more. The little ole M1 in a mac mini, starting at $700 has at least 8 memory channels. So basically the M1 delivers on all fronts, larger and lower latency caches, wide issue, large reorder buffers, excellent IPC, and excellent power efficiency.
Re: Memory access on the Apple M1 processor
#234Earlier quoted context omitted.
> There's not enough info to figure out what's going on. If you only look at the article this is true. However, the source code is freely available: https://github.com/lemire/Code-used-on-Daniel-Lemire-s-blog/...
I ran the benchmark on my system It's a 6 years old system, fastest times are in the 25ns range - 2-wise+ is 5% slower than 2-wise - 3-wise is 46% slower than 2-wise - 3-wise is 39% slower than 2-wise+ on the M1 - 2-wise+ is 40% slower than 2-wise - 3-wise is 46% slower than 2-wise - 3-wise is 4% slower than 2-wise+
Ouch. This is on my $2500 i5 mbpro from 2018.
$ ./two_or_three
N = 1000000000, 953.7 MB
starting experiments.
two : 53.3 ns
two+ : 60.1 ns
three: 78.6 ns
bogus 1375316400
------
2+ 12% slower than 2
3-wise 47% slower than 2
3-wise 30% slower than 2+
-------
Ratios aside, that's an interesting speed leap when the article gets 9 ms for 2-wise. Mind, the laptop had lots of applications running, i didn't clear it up to do a proper benchmark, but still.
Re: Memory access on the Apple M1 processor
#235Earlier quoted context omitted.
As WMF mentions, Tiger Lake laptops like my Razer Book have the same memory. It is not appreciably closer to the CPU in the Apple design. In Intel's Tiger Lake reference designs the memory is also in two chips that are mounted right next to the CPU.
I have a Dell XPS 13 with a Tiger Lake CPU. Out of curiosity, running the script: > ./two_or_three N = 1000000000, 953.7 MB starting experiments. two : 30.6 ns two+ : 39.6 ns three: 45.1 ns bogus 1422321000 This is much slower than the times Lemire reported for the M1. `two+` is 62% of the way between `two` and and `three`, vs 88% for the M1. EDIT: Adding `-march=native` didn't really change the results, which makes…
Strange on my XPS 15 7590 (i7-9750H), I get
N = 1000000000, 953.7 MB
starting experiments.
two : 12.8 ns
two+ : 13.7 ns
three: 19.5 ns
bogus 1422321000Re: Memory access on the Apple M1 processor
#236Earlier quoted context omitted.
Microsoft doesn't need to acquire Intel, they need to do what Apple did and acquire a stellar ARM design house that will build a chip with x86 translation, tailored to accelerate the typical workloads on Windows machines and sell those chips to the likes of Dell and Lenovo and tell developers "ARM Windows is the future, x86 Windows will be sunset in 5 years and no longer supported by us, start porting your apps ASAP…
Microsoft has a pretty good relationship with AMD from the Xbox. AMD already made an Arm Opteron. Windows has been multiplatform since NT 3.1 (Alpha, MIPS) and then in 3.51 adding in PowerPC. You can download Windows for Arm for free and run in on a Raspberry Pi. Microsoft has at least one homegrown processor that it has ported Windows and Linux to with the confusingly named 'Edge'. https://www.theregister.com/2018/0…
> Windows has been multiplatform since NT 3.1 (Alpha, MIPS) and then in 3.51 adding in PowerPC.
What was the last version of Windows to support either of these platforms?
Re: Memory access on the Apple M1 processor
#237Earlier quoted context omitted.
I have a Dell XPS 13 with a Tiger Lake CPU. Out of curiosity, running the script: > ./two_or_three N = 1000000000, 953.7 MB starting experiments. two : 30.6 ns two+ : 39.6 ns three: 45.1 ns bogus 1422321000 This is much slower than the times Lemire reported for the M1. `two+` is 62% of the way between `two` and and `three`, vs 88% for the M1. EDIT: Adding `-march=native` didn't really change the results, which makes…
Strange on my XPS 15 7590 (i7-9750H), I get N = 1000000000, 953.7 MB starting experiments. two : 12.8 ns two+ : 13.7 ns three: 19.5 ns bogus 1422321000
Yeah, that is strange. Why was it so slow?
Trying on a desktop with a 7900X, I get
N = 1000000000, 953.7 MB
starting experiments.
two : 17.7 ns
two+ : 19.1 ns
three: 26.4 ns
bogus 1422321000
Re: Memory access on the Apple M1 processor
#238Re: Memory access on the Apple M1 processor
#239I can't find any info about the memory bus of apple m1. Is it 8 channels 16 bit each? That's drastically different from AMDs 2 channels 64 bit each. It looks like apple m1 is much less eager when caching memory rows. Maybe because it doesn't have l3 cache. Edit: This test utilizes the 8x16bit memory bus of apple m1 fully. It's mostly just fetching random locations from memory, which can all be parallelized by the cpu…
That would make sense for LPDDR4 but it apparently claims to have a 128 byte cache line size and I'm not sure how to square that with 16 bit channel width.
Re: Memory access on the Apple M1 processor
#240Earlier quoted context omitted.
I have a Dell XPS 13 with a Tiger Lake CPU. Out of curiosity, running the script: > ./two_or_three N = 1000000000, 953.7 MB starting experiments. two : 30.6 ns two+ : 39.6 ns three: 45.1 ns bogus 1422321000 This is much slower than the times Lemire reported for the M1. `two+` is 62% of the way between `two` and and `three`, vs 88% for the M1. EDIT: Adding `-march=native` didn't really change the results, which makes…
Strange on my XPS 15 7590 (i7-9750H), I get N = 1000000000, 953.7 MB starting experiments. two : 12.8 ns two+ : 13.7 ns three: 19.5 ns bogus 1422321000
I just ran it again, and got more or less the same results:
N = 1000000000, 953.7 MB
starting experiments.
two : 29.7 ns
two+ : 36.5 ns
three: 43.8 ns
Looking a little closer at the script, it loads numbers from "random", a vector of 3 million `Int` (this is hard coded, separate from `N`). This vector is about 11.4 MiB.
The Tiger Lake CPU has 12 MiB of L3 cache (same as your i7-9750H), so it barely fits. Meanwhile, the L1 cache is 48 KiB and the L2 cache is 1.5 MiB -- huge compared to most recent CPUS, and a lot of benefit in most benchmarks, but at the cost of higher latency. https://www.anandtech.com/show/16084/intel-tiger-lake-review...
Skylake's L3 latency was 26-37 cycles, and in Willow Cove's (Tiger Lake), it is 39-45 cycles. That difference by itself isn't big enough to account for the difference we're seeing, so something else must be going on.