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Memory access on the Apple M1 processor

lemire.me

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Re: Memory access on the Apple M1 processor

#131

Post by [deleted] »

FabHK wrote: post #98
kllrnohj wrote: post #83

Earlier quoted context omitted.

How are you defining memory performance and where are your supporting comparisons? This article only discusses the M1's behavior, and makes no comparisons to any other CPU.

FWIW, I ran it on a MacBook Pro (13-inch, 2019, Four Thunderbolt 3 ports), 2.4 GHz Quad-Core Intel Core i5, 8 GB 2133 MHz LPDDR3: two : 49.6 ns (x 5.5) two+ : 64.8 ns (x 5.2) three: 72.8 ns (x 5.6) EDIT to add: above was just `cc`. Below is with `cc -O3 -Wall`, as in Lemire's article: two : 62.8 ns (x 7.1) two+ : 69.2 ns (x 5.5) three: 95.3 ns (x 7.3)

[deleted]

Re: Memory access on the Apple M1 processor

#132

Post by africanboy »

FabHK wrote: post #98
kllrnohj wrote: post #83

Earlier quoted context omitted.

How are you defining memory performance and where are your supporting comparisons? This article only discusses the M1's behavior, and makes no comparisons to any other CPU.

FWIW, I ran it on a MacBook Pro (13-inch, 2019, Four Thunderbolt 3 ports), 2.4 GHz Quad-Core Intel Core i5, 8 GB 2133 MHz LPDDR3: two : 49.6 ns (x 5.5) two+ : 64.8 ns (x 5.2) three: 72.8 ns (x 5.6) EDIT to add: above was just `cc`. Below is with `cc -O3 -Wall`, as in Lemire's article: two : 62.8 ns (x 7.1) two+ : 69.2 ns (x 5.5) three: 95.3 ns (x 7.3)

there must be something wrong there, on my late 2014 laptop that mounts

    Type: DDR4
    Speed: 2133 MT/s
I get

    two  : 27.1 ns (3x)
    two+ : 28.6 ns (2.2x)
    three: 39.7 ns (3x)
which is not much, considering this is an almost 6 years old system with 2x slower memor

Re: Memory access on the Apple M1 processor

#133

Post by GeekyBear »

adam_arthur wrote: post #94
pdpi wrote: post #20

Earlier quoted context omitted.

This seems to be a recurring theme with the M1, and one that, in a sense, actually baffles me even more than the alternative. There is no "magic" at play here, it's just lots and lots of raw muscle. They just seem to have a freakishly successful strategy for choosing what aspects of the processor to throw that muscle at. Why is that strategy simultaneously remarkably efficient and remarkably high-performance? What en…

Certainly Apple's processors are far ahead, but they're a full process generation (5nm) ahead of their competitors. They paid their way to that exclusive right through TSMC. I'm sure they'll still come out ahead in benchmarks, but the numbers will be much closer once AMD moves to 5nm. You absolutely cannot fairly compare chips from different fab generations. I don't see many comments hammering this point home enough.…

A node shrink gives you a choice of cutting power, improving performance, or some mix of the two.

Apple appears to have taken the power reduction when they moved to TSMC 5nm.

>The one explanation and theory I have is that Apple might have finally pulled back on their excessive peak power draw at the maximum performance states of the CPUs and GPUs, and thus peak performance wouldn’t have seen such a large jump this generation, but favour more sustainable thermal figures.

Apple’s A12 and A13 chips were large performance upgrades both on the side of the CPU and GPU, however one criticism I had made of the company’s designs is that they both increased the power draw beyond what was usually sustainable in a mobile thermal envelope. This meant that while the designs had amazing peak performance figures, the chips were unable to sustain them for prolonged periods beyond 2-3 minutes. Keeping that in mind, the devices throttled to performance levels that were still ahead of the competition, leaving Apple in a leadership position in terms of efficiency.

https://www.anandtech.com/show/16088/apple-announces-5nm-a14...

Re: Memory access on the Apple M1 processor

#134

Post by mrob »

SekstiNi wrote: post #26
phkahler wrote: post #21

Earlier quoted context omitted.

>> My understanding, based on the article, is that a normal processor, we would have expected arr[idx] + arr[idx+1] and arr[idx] to take the same amount of time. That depends. If the two accesses are on the same cache line, then yes. But since idx is random that will not happen sometimes. He never says how big array[] is in elements or what size each element is. I thought DRAM also had the ability to stream out conse…

> There's not enough info to figure out what's going on. If you only look at the article this is true. However, the source code is freely available: https://github.com/lemire/Code-used-on-Daniel-Lemire-s-blog/...

I tried it on my old (2009) 2.5GHz Phenom II X4 905e (GCC 10.2.1 -O3, 64 bit) and got results almost perfectly matching the conventional wisdom:

  two  : 97.4 ns
  two+  : 97.9 ns
  three: 145.8 ns

Re: Memory access on the Apple M1 processor

#135

Post by martamorena2 »

jeffbee wrote: post #79
pdpi wrote: post #20

Earlier quoted context omitted.

This seems to be a recurring theme with the M1, and one that, in a sense, actually baffles me even more than the alternative. There is no "magic" at play here, it's just lots and lots of raw muscle. They just seem to have a freakishly successful strategy for choosing what aspects of the processor to throw that muscle at. Why is that strategy simultaneously remarkably efficient and remarkably high-performance? What en…

I don't have any inside-Apple perspective, but my guess is having a tight feedback cycle between the profiles of their own software and the abilities of their own hardware has helped them greatly. The reason I think so is when I was at Google is was 7 years between when we told Intel what could be helpful, and when they shipped hardware with the feature. Also, when AMD first shipped the EPYC "Naples" it was crippled…

That's bizarre. As if CPU vendors were unable to run "realistic" workloads. If they truly aren't, that's because they are unwilling and then they are designing for failure and Apple can just eat their lunch.

Re: Memory access on the Apple M1 processor

#136

Post by SAI_Peregrinus »

jeffbee wrote: post #112
danaris wrote: post #100

Earlier quoted context omitted.

And (genuine question) how do the Tiger Lake laptops compare with the M1 MacBooks thus far?

The outcome seems to depend greatly on the physical design of the laptops. The elsewhere-mentioned Dell XPS 13 has a particularly poor cooling design, which is why I chose the Razer Book instead. Despite being marketed in a very silly way to gamers only, it seems to have competent mechanical design.

Gamers are likely to run their systems with demanding workloads, for hours, with a color-coded performance counter (FPS stat). They'll notice if it throttles. They're particularly demanding customers, and there's quite a bit of competition for their money.

Re: Memory access on the Apple M1 processor

#137

Post by sliken »

tandr wrote: post #117
sliken wrote: post #89

Earlier quoted context omitted.

The most impressive thing I've seen is that when accessed in a TLB friendly fashion that the latency is around 30ns. Anandtech has a graph showing this, specifically the R per RV prange graph. I've verified this personally with a small microbenchmark I wrote. I've not seen anything else close to this memory latency.

Sorry, what would AMD's or Intel's "latest and greatest" numbers for the same be?

Here's the M1: https://www.anandtech.com/show/16252/mac-mini-apple-m1-teste...

Scroll down to the latency vs size map and look at the R per RV prange. That gets you 30ns or so.

Similar for AMD's latest/greatest the Ryzen 9 5950X: https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-di...

The same R per RV prange is in the 60ns range.

Re: Memory access on the Apple M1 processor

#138

Post by ralfd »

ChuckNorris89 wrote: post #127
dcolkitt wrote: post #106

Earlier quoted context omitted.

Interesting point. This would suggest pretty sizable synergies from the oft-rumored Microsoft acquisition of Intel.

Microsoft doesn't need to acquire Intel, they need to do what Apple did and acquire a stellar ARM design house that will build a chip with x86 translation, tailored to accelerate the typical workloads on Windows machines and sell those chips to the likes of Dell and Lenovo and tell developers "ARM Windows is the future, x86 Windows will be sunset in 5 years and no longer supported by us, start porting your apps ASAP…

Apple has at most 10% of the computer market and is just one player among many. I am skeptical Microsoft with their 90% dominance would or should be allowed this much power over the industry.

Re: Memory access on the Apple M1 processor

#140

Post by sliken »

reasonabl_human wrote: post #124
sliken wrote: post #89

Earlier quoted context omitted.

The most impressive thing I've seen is that when accessed in a TLB friendly fashion that the latency is around 30ns. Anandtech has a graph showing this, specifically the R per RV prange graph. I've verified this personally with a small microbenchmark I wrote. I've not seen anything else close to this memory latency.

Mind sharing the micro benchmark you wrote? I’m curious to know how that would work

https://github.com/spikebike/pstream

It's designed to graph latency/bandwidth for 1 to N threads. My 1 thread numbers match Anandtech's. Use -p 0 for full random, which thrashes the TLB or -p 1 to be cache friendly (visit each cacheline once, but within a sliding window of 1 page).

To see the apple results (if you have gnuplot installed): ./lview results/apple-m1

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