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Memory access on the Apple M1 processor

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Re: Memory access on the Apple M1 processor

#101

Post by jandrese »

pdpi wrote: post #20
jeffbee wrote: post #2

Great practical information. Nice to see people who know what they are talking about putting data out there. I hope eventually these persistent HN memes about M1 memory will die: that it's "on-die" (it's not), that it's the only CPU using LPDDR4X-4267 (it's not), or that it's faster because the memory is 2mm closer to the CPU (not that either). It's faster because it has more microarchitectural resources. It can load…

This seems to be a recurring theme with the M1, and one that, in a sense, actually baffles me even more than the alternative. There is no "magic" at play here, it's just lots and lots of raw muscle. They just seem to have a freakishly successful strategy for choosing what aspects of the processor to throw that muscle at. Why is that strategy simultaneously remarkably efficient and remarkably high-performance? What en…

It seems like Apple listened when people talked about how all modern processors bottleneck on memory access and decided to focus heavily on getting those numbers better.

Of course this leads to the question that if everyone in the industry knew this was the issue why weren't Intel and AMD pushing harder on it? They already both moved the memory controller onboard so they had the opportunity to aggressively optimize it like Apple has done, but instead we have year after year where the memory lags behind the processor in speed improvements, to the point where it is ridiculous how many clock cycles a main memory access takes on a modern x86 chip.

Re: Memory access on the Apple M1 processor

#102

Post by foldr »

jeffbee wrote: post #2

Great practical information. Nice to see people who know what they are talking about putting data out there. I hope eventually these persistent HN memes about M1 memory will die: that it's "on-die" (it's not), that it's the only CPU using LPDDR4X-4267 (it's not), or that it's faster because the memory is 2mm closer to the CPU (not that either). It's faster because it has more microarchitectural resources. It can load…

>or that it's faster because the memory is 2mm closer to the CPU (not that either)

Not to disagree with your overall point, but 2mm is a long way when dealing with high frequency signals. You can't just eyeball this and infer that it makes no difference to performance or power consumption.

Re: Memory access on the Apple M1 processor

#103

Post by foota »

hundchenkatze wrote: post #60
foota wrote: post #28

Is this per core or shared between cores?

Per core I think, emphasis is mine. > It looks like a single core has about 28 levels of memory parallelism, and possibly more.

I was wondering if this might be a shared resource though, since it doesn't seem they tested with multiple threads.

Re: Memory access on the Apple M1 processor

#104

Post by adam_arthur »

PragmaticPulp wrote: post #96
jeffbee wrote: post #2

Great practical information. Nice to see people who know what they are talking about putting data out there. I hope eventually these persistent HN memes about M1 memory will die: that it's "on-die" (it's not), that it's the only CPU using LPDDR4X-4267 (it's not), or that it's faster because the memory is 2mm closer to the CPU (not that either). It's faster because it has more microarchitectural resources. It can load…

I don't understand this competition to attribute the M1's speed to one specific change, while downplaying all of the others. M1 is fast because they optimized everything across the board. The speed is the cumulative result of many optimizations, from the on-die memory to the memory clock speed to the architecture.

It's fast because they optimized everything across the board, and also paid for exclusive access to TSMC 5nm process.

Re: Memory access on the Apple M1 processor

#105

Post by jayd16 »

wrsh07 wrote: post #51
jayd16 wrote: post #40

Earlier quoted context omitted.

I don't really understand the comparison because it seems like scenario 3 (2+) is doing more XORs and twice the accesses to array over the same amount of iterations. We have to assume these are byte arrays, yes? Or at least some size that's smaller than the cache line. You would still pay for the extra unaligned fetches. I don't think this is a valid scenario at all, M1 or not. Anyone want to run these tests on an In…

The point of the naive model is that you assume memory accesses dominate That is, the math part is so trivial compared to the memory access that you could do a bunch of math and you would still only notice a change in the number of memory accesses. Also it looks like the response to yours links their test and the naive model predicts correctly

I think 5% is a non-trivial difference but alright, its a much bigger difference on the M1.

I guess I still don't understand whats going on here.

Scenario 1 has two spatially close reads followed by two dependent random access reads.

Scenario 3 (2+) has two spatially close reads, and two pairs of dependent random access reads of two spatially close locations.

Why does it follow that this is caused by a change in memory access concurrency? The two required round trips should dominate both on the M1 and an Intel but for some reason the M1 performs worse than that. Why?

I can't help but feel the first snippet triggers some SIMD path while the 3rd snippet fails to.

Re: Memory access on the Apple M1 processor

#106

Post by dcolkitt »

jeffbee wrote: post #79
pdpi wrote: post #20

Earlier quoted context omitted.

This seems to be a recurring theme with the M1, and one that, in a sense, actually baffles me even more than the alternative. There is no "magic" at play here, it's just lots and lots of raw muscle. They just seem to have a freakishly successful strategy for choosing what aspects of the processor to throw that muscle at. Why is that strategy simultaneously remarkably efficient and remarkably high-performance? What en…

I don't have any inside-Apple perspective, but my guess is having a tight feedback cycle between the profiles of their own software and the abilities of their own hardware has helped them greatly. The reason I think so is when I was at Google is was 7 years between when we told Intel what could be helpful, and when they shipped hardware with the feature. Also, when AMD first shipped the EPYC "Naples" it was crippled…

Interesting point. This would suggest pretty sizable synergies from the oft-rumored Microsoft acquisition of Intel.

Re: Memory access on the Apple M1 processor

#107

Post by danaris »

marrvelous wrote: post #99
fartcannon wrote: post #92

Earlier quoted context omitted.

They could still do all this shit without the walled garden. To me, it suggests they aren't willing to compete. They're anti-competitive.

With the walled garden, Apple can set enforceable timelines for the software ecosystem to adopt to architectural changes. Remember the transition to arm64? Apple forced everything on the App Store to ship universal binaries. Without the App Store walled garden, software isn’t required to keep up to date with architectural changes. Instead, keeping current is only a requirement to being featured on the App Store (whic…

Well, and on the Mac, it's not the only method. The walled garden here has big open gates.

That said, all software on the Mac, post-Catalina, has to be 64-bit, whether it's distributed through the Mac App Store or not, because the 32-bit system libraries are no longer included at all.

Re: Memory access on the Apple M1 processor

#108

Post by skavi »

danaris wrote: post #100
jeffbee wrote: post #69

Earlier quoted context omitted.

As WMF mentions, Tiger Lake laptops like my Razer Book have the same memory. It is not appreciably closer to the CPU in the Apple design. In Intel's Tiger Lake reference designs the memory is also in two chips that are mounted right next to the CPU.

And (genuine question) how do the Tiger Lake laptops compare with the M1 MacBooks thus far?

AnandTech has decent benchmarks for both Tiger Lake [0] and M1 [1].

[0]: https://www.anandtech.com/show/16084/intel-tiger-lake-review...

[1]: https://www.anandtech.com/show/16252/mac-mini-apple-m1-teste...

Re: Memory access on the Apple M1 processor

#109

Post by ksec »

tyingq wrote: post #71
Bootvis wrote: post #54

Earlier quoted context omitted.

What is a KOL?

"Key Opinion Leader". I think it's the new word for "Influencer".

I am pretty sure KOL predates Influencer in modern internet usage. Before that they were simply known as Internet Celebrities. May be it is rarely used now. So apology for not explaining the acronyms.

Re: Memory access on the Apple M1 processor

#110

Post by namibj »

FabHK wrote: post #98
kllrnohj wrote: post #83

Earlier quoted context omitted.

How are you defining memory performance and where are your supporting comparisons? This article only discusses the M1's behavior, and makes no comparisons to any other CPU.

FWIW, I ran it on a MacBook Pro (13-inch, 2019, Four Thunderbolt 3 ports), 2.4 GHz Quad-Core Intel Core i5, 8 GB 2133 MHz LPDDR3: two : 49.6 ns (x 5.5) two+ : 64.8 ns (x 5.2) three: 72.8 ns (x 5.6) EDIT to add: above was just `cc`. Below is with `cc -O3 -Wall`, as in Lemire's article: two : 62.8 ns (x 7.1) two+ : 69.2 ns (x 5.5) three: 95.3 ns (x 7.3)

You _need_ to use -mnative because it otherwise retains backwards compatibility to older x86.
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