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Memory access on the Apple M1 processor

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Re: Memory access on the Apple M1 processor

#81

Post by fluffy87 »

sroussey wrote: post #48
jayd16 wrote: post #27

>our naive random-memory model Doesn't everyone use the (I believe) still valid concepts of latency and bandwidth?

Depends on context. For example, what is the bandwidth and latency when you ask for the value at the same memory address in an infinite loop? And how does that compare to the latency and bandwidth of a memory module you buy on NewEgg?

L1 BW.

When people use BW in their performance models, they don’t use only 1 bandwidth, but whatever combination of bandwidth makes sense for the _memory access pattern_.

So if you are always accessing the same word, the first acces runs at DRAM BW, and subsequent ones at L1 BW, and any meaningful performance model will take that into account.

Re: Memory access on the Apple M1 processor

#82

Post by titzer »

jeffbee wrote: post #73
titzer wrote: post #63

Earlier quoted context omitted.

Sure, and it has a very large out-of-order execution engine, but it is not fundamentally different from what other super scalar processors do. So I am curious what the OP meant by that offhand comment.

One core of the M1 can drive the memory subsystem to the rails. A single core can copy (load+store) at 60GB/s. This is close to the theoretical design limit for DDR4X. A single core on Tiger Lake can only hit about 34GB/s, and Skylake-SP only gets about 15GB/s. So yes, it is close to 4x faster.

Thanks for clarifying. But this isn't any fundamental difference IMO. There isn't any functional limitation in an Intel core that means it cannot saturate the memory bandwidth from a single core, unless I am missing something.

Re: Memory access on the Apple M1 processor

#83

Post by kllrnohj »

saagarjha wrote: post #77
temac wrote: post #57

Earlier quoted context omitted.

It is not 4 times faster than an Intel core, though...

It is in memory performance, which is what I assumed was being measured here.

How are you defining memory performance and where are your supporting comparisons? This article only discusses the M1's behavior, and makes no comparisons to any other CPU.

Re: Memory access on the Apple M1 processor

#85

Post by jeffbee »

titzer wrote: post #82
jeffbee wrote: post #73

Earlier quoted context omitted.

One core of the M1 can drive the memory subsystem to the rails. A single core can copy (load+store) at 60GB/s. This is close to the theoretical design limit for DDR4X. A single core on Tiger Lake can only hit about 34GB/s, and Skylake-SP only gets about 15GB/s. So yes, it is close to 4x faster.

Thanks for clarifying. But this isn't any fundamental difference IMO. There isn't any functional limitation in an Intel core that means it cannot saturate the memory bandwidth from a single core, unless I am missing something.

I agree, it's not fundamental. It is, in particular, not that other popular myth, that it's "because ARM". It's only that 1 core on an Intel chip can have N-many outstanding loads and 1 core of an M1 can have M>N outstanding loads.

Re: Memory access on the Apple M1 processor

#86

Post by kllrnohj »

amelius wrote: post #55
ed25519FUUU wrote: post #18

Earlier quoted context omitted.

In other words, it’s better architecture. If anything this makes it seem more impressive to me.

No, it's the same architecture but with different parameters. It's like the difference between the situation where every car uses 4 cylinders, and then Apple comes along and makes a car with 5 cylinders.

Your analogy was so close! It's Apple comes along and makes an 8 cylinder engine. Since, you know, the other CPUs are 4-wide decode and Apple's M1 is 8-wide decode :)

Re: Memory access on the Apple M1 processor

#87

Post by gavin_gee »

pdpi wrote: post #20
jeffbee wrote: post #2

Great practical information. Nice to see people who know what they are talking about putting data out there. I hope eventually these persistent HN memes about M1 memory will die: that it's "on-die" (it's not), that it's the only CPU using LPDDR4X-4267 (it's not), or that it's faster because the memory is 2mm closer to the CPU (not that either). It's faster because it has more microarchitectural resources. It can load…

This seems to be a recurring theme with the M1, and one that, in a sense, actually baffles me even more than the alternative. There is no "magic" at play here, it's just lots and lots of raw muscle. They just seem to have a freakishly successful strategy for choosing what aspects of the processor to throw that muscle at. Why is that strategy simultaneously remarkably efficient and remarkably high-performance? What en…

didnt they also make some interesting hires a few years ago like Anand from Anandtech and some other silicon vets that likely helped them design the M1 approach?

Re: Memory access on the Apple M1 processor

#89

Post by sliken »

jeffbee wrote: post #2

Great practical information. Nice to see people who know what they are talking about putting data out there. I hope eventually these persistent HN memes about M1 memory will die: that it's "on-die" (it's not), that it's the only CPU using LPDDR4X-4267 (it's not), or that it's faster because the memory is 2mm closer to the CPU (not that either). It's faster because it has more microarchitectural resources. It can load…

The most impressive thing I've seen is that when accessed in a TLB friendly fashion that the latency is around 30ns.

Anandtech has a graph showing this, specifically the R per RV prange graph. I've verified this personally with a small microbenchmark I wrote. I've not seen anything else close to this memory latency.

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