Project Oberon 2013 on RISC-V
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Project Oberon 2013 on RISC-V
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Re: Project Oberon 2013 on RISC-V
#2Hi,
this port of Niklaus Wirth's Project Oberon (http://www.projectoberon.com) to RISC-V (rv32im) is the semester project of my student Rikke Solbjørg at the department of computer science at NTNU in Trondheim/Norway.
The system currently runs in a version of Peter de Wachter's emulator modified to use a RISC-V CPU emulation instead of Wirth's RISC5 (now isn't that confusing? ;-)).
Rikke's announcement on the Oberon mailing list: http://lists.inf.ethz.ch/pipermail/oberon/2020/015269.html
To answer the obvious question right away: yes, we are working on a FPGA implementation :-). Happy to answer your other questions...
Re: Project Oberon 2013 on RISC-V
#3Hi, this port of Niklaus Wirth's Project Oberon ( http://www.projectoberon.com ) to RISC-V (rv32im) is the semester project of my student Rikke Solbjørg at the department of computer science at NTNU in Trondheim/Norway. The system currently runs in a version of Peter de Wachter's emulator modified to use a RISC-V CPU emulation instead of Wirth's RISC5 (now isn't that confusing? ;-)). Rikke's announcement on the Obero…
Just to congratulate everyone involved.
Any thoughts about pursuing similar endeavours with System 3?
System 3 is closer to modern systems in L&F, which could make some students feel more inspired to delve into Oberon based platforms.
Just as an idea for other upcoming projects, I guess.
Re: Project Oberon 2013 on RISC-V
#4Hi, this port of Niklaus Wirth's Project Oberon ( http://www.projectoberon.com ) to RISC-V (rv32im) is the semester project of my student Rikke Solbjørg at the department of computer science at NTNU in Trondheim/Norway. The system currently runs in a version of Peter de Wachter's emulator modified to use a RISC-V CPU emulation instead of Wirth's RISC5 (now isn't that confusing? ;-)). Rikke's announcement on the Obero…
Just to congratulate everyone involved. Any thoughts about pursuing similar endeavours with System 3? System 3 is closer to modern systems in L&F, which could make some students feel more inspired to delve into Oberon based platforms. Just as an idea for other upcoming projects, I guess.
We are currently discussing a number of ideas for a followup project in addition to creating an FPGA version...
I'm currently digging through the 1992/2005 edition of the Project Oberon book (for the National Semiconductor 32k-based Ceres workstations from ETHZ - https://people.inf.ethz.ch/wirth/ProjectOberon1992.pdf). The Ceres Oberon version had a number of additional features, e.g. it could use the MMU for memory protection, which the RISC5 version doesn't support.
Re: Project Oberon 2013 on RISC-V
#5Hi, this port of Niklaus Wirth's Project Oberon ( http://www.projectoberon.com ) to RISC-V (rv32im) is the semester project of my student Rikke Solbjørg at the department of computer science at NTNU in Trondheim/Norway. The system currently runs in a version of Peter de Wachter's emulator modified to use a RISC-V CPU emulation instead of Wirth's RISC5 (now isn't that confusing? ;-)). Rikke's announcement on the Obero…
How much memory does it require to run?
Re: Project Oberon 2013 on RISC-V
#6Hi, this port of Niklaus Wirth's Project Oberon ( http://www.projectoberon.com ) to RISC-V (rv32im) is the semester project of my student Rikke Solbjørg at the department of computer science at NTNU in Trondheim/Norway. The system currently runs in a version of Peter de Wachter's emulator modified to use a RISC-V CPU emulation instead of Wirth's RISC5 (now isn't that confusing? ;-)). Rikke's announcement on the Obero…
How much memory does it require to run?
The original Wirth RISC5 version runs in 1 MB RAM on an ancient Xilinx FPGA board. The RISC-V binaries are a bit larger, but still runs in 1 MB (but more is possible). A bit too large for typical block RAM sizes of affordable FPGAs, unfortunately.
Some details on the port and the binary size differences can be found in the project report: https://github.com/solbjorg/oberon-riscv/blob/master/report....
Re: Project Oberon 2013 on RISC-V
#7Earlier quoted context omitted.
How much memory does it require to run?
The original Wirth RISC5 version runs in 1 MB RAM on an ancient Xilinx FPGA board. The RISC-V binaries are a bit larger, but still runs in 1 MB (but more is possible). A bit too large for typical block RAM sizes of affordable FPGAs, unfortunately. Some details on the port and the binary size differences can be found in the project report: https://github.com/solbjorg/oberon-riscv/blob/master/report....
"block ram" (like iCE40's sysMEM) is usually very fast, fancy and dual port, which is why there's so little of it, and is typically spread across the die for reduced latency purposes.
From a CPU-in-FPGA perspective, it could be used for e.g. L1 cache. Actual RAM can be slower and external to the FPGA chip.
The ULX3S (which can support the minimig Amiga implementation) and the DE10-Nano (miSTer's base board) would make overkill targets for this.
Re: Project Oberon 2013 on RISC-V
#8Earlier quoted context omitted.
The original Wirth RISC5 version runs in 1 MB RAM on an ancient Xilinx FPGA board. The RISC-V binaries are a bit larger, but still runs in 1 MB (but more is possible). A bit too large for typical block RAM sizes of affordable FPGAs, unfortunately. Some details on the port and the binary size differences can be found in the project report: https://github.com/solbjorg/oberon-riscv/blob/master/report....
"block ram" (like iCE40's sysMEM) is usually very fast, fancy and dual port, which is why there's so little of it, and is typically spread across the die for reduced latency purposes. From a CPU-in-FPGA perspective, it could be used for e.g. L1 cache. Actual RAM can be slower and external to the FPGA chip. The ULX3S (which can support the minimig Amiga implementation) and the DE10-Nano (miSTer's base board) would mak…
Of course, external RAM is an option. However, using external SDRAM increases the complexity of the hardware significantly, which takes away a bit of the elegance and simplicity of Wirth's original RISC5 FPGA system. Wirth's system used a Xilinx Spartan 3 board with 1 MB of 32 bit wide fast asynchronous SRAM (https://multicores.org/blog/small-is-beautiful.html).
Unfortunately, FPGA boards with 32 bit wide SRAM are really hard to find nowadays, especially those supported by SymbiFlow...
Re: Project Oberon 2013 on RISC-V
#9Hi, this port of Niklaus Wirth's Project Oberon ( http://www.projectoberon.com ) to RISC-V (rv32im) is the semester project of my student Rikke Solbjørg at the department of computer science at NTNU in Trondheim/Norway. The system currently runs in a version of Peter de Wachter's emulator modified to use a RISC-V CPU emulation instead of Wirth's RISC5 (now isn't that confusing? ;-)). Rikke's announcement on the Obero…
How much memory does it require to run?
I'd love to see a text-only version. That would be fun to develop against and almost any FPGA should be able to run it. Might evolve into an interesting embedded platform over time.
Re: Project Oberon 2013 on RISC-V
#10Earlier quoted context omitted.
How much memory does it require to run?
I'd love to see a text-only version. That would be fun to develop against and almost any FPGA should be able to run it. Might evolve into an interesting embedded platform over time.
Astrobe provides Oberon systems for embedded applications, there is currently a version using Wirth's RISC5 running on 7-series Xilinx FPGAs - https://www.astrobe.com/RISC5/
They also have a version for ARM Cortex-M controllers: https://www.astrobe.com/Oberon.htm