Live data from Hacker News

Show HN: NN-512 – Generate standalone C code for neural nets

nn-512.com

11–20 of 30 posts

Re: Show HN: NN-512 – Generate standalone C code for neural nets

#11

NN-512 is an open-source Go program that generates fully AVX-512 vectorized, human-readable, stand-alone C implementations of convolutional neural nets The generated C code is an example of AVX-512 programming using GCC's AVX-512 intrinsics. AVX-512 is exciting because its use of masking simplifies edge cases (partial loads, partial stores, etc.), there are 32 wide vector registers, and really excellent shuffle/permu…

Is there the option to use AVX2 (256-bit) instead of AVX-512 (which can cause thermal throttling on basically every chip[a])? Now, if Intel can get AVX-512 working well, that’s something else. Side question: do any Ryzen processors support AVX-512? AFAIK, they only support up to AVX2. [a]: IIRC, some tests show AVX2 code actually being faster than the equivalent AVX-512 code because AVX2 doesn’t cause the processor t…

No support for AVX2. AVX-512 is the first really nice (from the programmer's perspective) SIMD instruction set on x86-64 CPUs, and it's significantly different from what came before. AVX-512 is not just a wider version of AVX2

NN-512 explores the way Winograd and Fourier convolutions can be done when you have 32 512-bit vector registers. Four 8x8 Winograd tiles simultaneously, four 8x8 Fourier tiles interleaved to form a 16x16 tile for strided convolutions, and so on. These multi-tile operations don't work for AVX2, too few registers, each register too narrow

GCC has only very recently come into a state where it properly supports AVX-512. For example, before GCC 9.1, GCC would split FNMADD into xor-negation followed by FMADD (doing an extra xor, using an extra register for the negation constant, instead of just using the FNMADD instruction).

Eventually the hardware will mature, too

Re: Show HN: NN-512 – Generate standalone C code for neural nets

#13

Earlier quoted context omitted.

Out of curiosity, have you benchmarked this against some of the more standard NN libraries running on CPU?

No, the convolution generators were written to saturate the hardware For example, under ideal conditions (no out-of-register memory access, no waiting on dependencies) you can sustain 27 single-precision FMADDs per CPU-core per cycle on a particular Skylake-X (i.e., approx 1.7 _mm512_fmadd_ps per cycle, each yielding 16 multiply-adds) As soon as you start accessing memory, that number drops to about 20 FMADDs. With d…

> For example, NN-512 can exceed 48 effective FMADDs per cycle (on the 27 peak FMADD machine) with Winograd-Cook-Toom-Lavin, if the tensor is deep enough (enough channels)

Roughly how many channels do you need for this approach to be worthwhile?

Re: Show HN: NN-512 – Generate standalone C code for neural nets

#14
post #13

Earlier quoted context omitted.

No, the convolution generators were written to saturate the hardware For example, under ideal conditions (no out-of-register memory access, no waiting on dependencies) you can sustain 27 single-precision FMADDs per CPU-core per cycle on a particular Skylake-X (i.e., approx 1.7 _mm512_fmadd_ps per cycle, each yielding 16 multiply-adds) As soon as you start accessing memory, that number drops to about 20 FMADDs. With d…

> For example, NN-512 can exceed 48 effective FMADDs per cycle (on the 27 peak FMADD machine) with Winograd-Cook-Toom-Lavin, if the tensor is deep enough (enough channels) Roughly how many channels do you need for this approach to be worthwhile?

Enough that the data panel of the input tensor fills the thread's share of the L2 cache, and the output tensor is of similar depth

So it depends on the cache size, but you can think of it as being about 512 channels in, 512 channels out, something like that

Re: Show HN: NN-512 – Generate standalone C code for neural nets

#16
post #15

```` Copyright (C) 2019 [ 37ef ced3 3727 60b4 3c29 f9c6 dc30 d518 f4f3 4106 6964 cab4 a06f c1a3 83fd 090e ] ``` 37ef_ced3, I'm curious if is a signature? Is the idea to assert copyright which maintaining anonymity, until proof of ownership is required?

That's right, SHA-256 of my (unimportant) identity, with salt

Re: Show HN: NN-512 – Generate standalone C code for neural nets

#18
post #9

I've heard that heavy sustained AVX3 / AVX-512 workloads have the potential to damage CPU's [0][1]. Would running/testing/playing around this software potentially risk damaging my CPU? Or is this only a risk when overclocking? I'm not being facetious with this question at all - more genuine curiosity / responsible preventative caution for my own machines, because I'm very much interested in playing around with this i…

The reality is that AMD's CPUs don't yet properly support AVX-512, and Intel's CPUs provide good implementations (e.g., 3 cycle latency for the useful AVX-512 shuffle/permutes) with a big downclocking caveat

AVX-512 will be great, eventually

Re: Show HN: NN-512 – Generate standalone C code for neural nets

#19
post #17

I think this is a very interesting project. I am curious what direction you are going. Does it support dilated convolutions, like Wavenet uses? Can it implement transformers?

As for dilated (and also grouped, like ResNeXt) convolutions, there is full support

The dilated (general-purpose, fallback) convolution algorithm executes FMADDs not much slower than the 1x1 convolution. It makes slow im2col-style approaches unnecessary. Example here: https://nn-512.com/example/4

The idea is to split the input and dilated weight tensors up according to the stride, and then do 1x1 convolutions with accumulation at heightwise and widthwise offsets

No transformers at the moment. You can see what is supported here: https://nn-512.com/docs/graph

Post reply on HN