Earlier quoted context omitted.
so you're saying somehow Rosetta2 is looking at an x86 binary and figuring out exactly which portions of the program rely on the TSO ordering for correctness and then dynamically switches to weak ordering for parts that might be able to do without? I don't really know much about the internals of macOS but figuring out when there are applications for example running on two different cores (since TSO is only really nee…
No; it’s not explained very well but the M1 chip features hardware support for TSO which Rosetta2 uses. It’s really ‘Apple Silicon’ and not just ARM.
Yeah, I think that's key to understanding this. They are supporting a version of ARM ISA running that maintains TSO even though official ARM doesn't need to support TSO. I guess this is all to get better emulation performance and avoid those extra synchronization instructions that would have to be added by Rosetta if the silicon did not have TSO support.