This is really nice, riscv plus Wifi and BT will be a dream for hackers provided the chip and firmware is well documented. The datasheet is also in the comments ( https://mega.nz/file/nk41mSAL#R_d0njlKRb-aIoGuX6JXUB5eeflAdy... )(chinese pdf) : 160MHz 400k sram apparently single core.
Some reason this didn't work, someone made an English translation https://mega.nz/file/4VRGgLzK#YIzeMvj_Z-LayxY8KztL4WiifcmQYc...
ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
11–20 of 119 posts
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#12> Pricing will also be similar to ESP8266. How can they possibly sell these chips at these prices? This is impossibly cheap. You can’t even accuse them of trying to flood and control the market because they already own the market!
what market are you talking about? hobby projects market? that's for sure, but that's not where the big money is.
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#13> Pricing will also be similar to ESP8266. How can they possibly sell these chips at these prices? This is impossibly cheap. You can’t even accuse them of trying to flood and control the market because they already own the market!
what market are you talking about? hobby projects market? that's for sure, but that's not where the big money is.
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#14Nice. The XTensa cores always felt weird. Too bad they only included the I/M/C extensions - no floats, vectors, or atomics. And USB would be nice (nevermind, it has USB :D). But it's still very exciting. Maybe there'll be less conflict between ARM/XTensa/PIC32/etc. cores in the coming years.
Why do you need atomics on a single core device?
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#15Nice. The XTensa cores always felt weird. Too bad they only included the I/M/C extensions - no floats, vectors, or atomics. And USB would be nice (nevermind, it has USB :D). But it's still very exciting. Maybe there'll be less conflict between ARM/XTensa/PIC32/etc. cores in the coming years.
Why do you need atomics on a single core device?
>Load
>Modify register in memory
>>Interrupt happens and changes
>Write incorrect value back to .
These sorts of bugs can be pernicious to debug, and they are easy for novice developers to create.
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#16This is really nice, riscv plus Wifi and BT will be a dream for hackers provided the chip and firmware is well documented. The datasheet is also in the comments ( https://mega.nz/file/nk41mSAL#R_d0njlKRb-aIoGuX6JXUB5eeflAdy... )(chinese pdf) : 160MHz 400k sram apparently single core.
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#17It will be interesting to see which one gains critical mass in community use.
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#18[1] https://news.ycombinator.com/item?id=24877335
[2] https://news.ycombinator.com/item?id=24916086
Skimming over C3 datasheet, it seems it doesn't have DAC but has one I2S. BL602 has DAC but no I2S!
Re: ESP32-C3 WiFi and BLE RISC-V processor is pin-to-pin compatible with ESP8266
#19Earlier quoted context omitted.
Some reason this didn't work, someone made an English translation https://mega.nz/file/4VRGgLzK#YIzeMvj_Z-LayxY8KztL4WiifcmQYc...
The comment parent to yours had a closing parentheses and stuff after the link that broke it. The link for the Chinese pdf is https://mega.nz/file/nk41mSAL#R_d0njlKRb-aIoGuX6JXUB5eeflAdy...