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Intel Reinvents Transistors Using New 3-D Structure

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Re: Intel Reinvents Transistors Using New 3-D Structure

#61

Post by Symmetry »

daeken wrote: post #47
Symmetry wrote: post #42

Earlier quoted context omitted.

The number of things of a given size you can fit on a plane within distance R of you is proportional to R^2. The number of things you can fit in a three dimensional space is R^3. So as we utilize 3D more and more things will tend to be closer together.

They're closer together, but the distance traveled in total is the same. Imagine the transistors are pieces of paper, and you're drawing a line over them. If the paper is flat, then you're drawing a line of distance n , and the points are n apart. If you fold the ends of the paper together, then the points are 0 units apart (or near enough to make no matter), but that line still has a distance of n .

Oh, I think I get what your confusion is now. The signal doesn't have to travel up and over now any more than it did when everything was flat. The signal will travel up a few gate widths to the low resistance metal interconnect layers, travel a few tens or hundreds of gate widths sideways to get to the next transistor, then goes down again to make the connection. Going to 3D doesn't change this except to make the up and down slightly longer and sideways much shorter.

Re: Intel Reinvents Transistors Using New 3-D Structure

#62

Post by bradly »

megaframe wrote: post #53
bradly wrote: post #11

Anyone know if the 3D structure is patented by Intel? If so, wouldn't this give Intel a monopoly on transistors given how much better this new design performs?

No this design was developed back when I was in college, the revolutionary change here is that Intel has a process to actually manufacture these things effectively and get decent yield. IBM had these things built in test cases back in 2007 but didn't have a manufacturing method. Intel will likely not patent or reveal the manufacturing method thats how most semiconductor manufacturing technologies go. They tend to be…

Thanks, that makes sense. I did find this patent from Intel about manufacturing the 3D transistor: http://www.google.com/patents?id=1D2gAAAAEBAJ&printsec=a...

Re: Intel Reinvents Transistors Using New 3-D Structure

#64

Post by [deleted] »

wtracy wrote: post #59
absconditus wrote: post #50

Earlier quoted context omitted.

Why do you need to keep up?

As a consumer he might not have any good reason to do so, but look at it from Intel's perspective: They're potentially not getting the best return on their R&D investment by encouraging customers to regularly skip generations.

[deleted]

Re: Intel Reinvents Transistors Using New 3-D Structure

#65

Post by tesseract »

ajross wrote: post #23
stephenjudkins wrote: post #14

From what I've heard, using 50% as much power for the same performance as the previous generation still will not be sufficient to bring Intel's Atom performance/energy consumption ratio to that offered by ARM chips. However, it's a huge leap in the right direction. Add better-designed power-saving features on the next generation of Atom chips, and future process shrinkages, and it's easy to see ARM's lead getting chi…

This is orthogonal. An ARM Cortex (or GPU, or whatever) on this process would see similar gains. It's also worth pointing out that current Atoms in the market are still 45nm parts, not even 32nm. Intel, for obvious reasons, tends to prioritize production of high-margin desktop and server CPUs over low-margin embedded parts. Really, this announcement isn't about ARM-based vs. Intel-based SoC designs. I think it's clea…

> This is about Intel cementing and extending its complete and total dominance of high end digital logic fabrication.

Given that, (and given that Intel has been dominant in process technology for some time now) I've always wondered why Intel doesn't do fabrication for third party, high-performance/high-margin/high-power-budget products that don't directly compete with Intel's main CPU product line. Networking/telecom processors, top-end FPGAs, DSPs, and so forth. Is it just that they are at capacity making CPUs and don't see any need to get into that business? Or do they do it already and I'm just not aware?

Re: Intel Reinvents Transistors Using New 3-D Structure

#66

Post by nightlifelover »

vondur wrote: post #29

I often wonder at the incredibly small size of these chips (22nm) if the have to worry about relativistic effects of electrons "jumping".

The quantum tunneling effect [1] is what you are referring to, right?

[1] http://en.wikipedia.org/wiki/Quantum_tunnelling

Re: Intel Reinvents Transistors Using New 3-D Structure

#68

Post by tspiteri »

repiret wrote: post #33
tspiteri wrote: post #10

Earlier quoted context omitted.

That may be true for a processor, but when talking about transistors, I think that clock speed and power consumption are the metrics to measure.

I would argue that neither of those things are metrics to measure for a transistor, since they are affected by how its used. Properties of the transistor itself are what matter: size, drain and source capacitance, leakage current when off, drain-source voltage drop when on, and probably a dozen things I don't really know about.

The properties you mention are mainly "low level" properties, which in the end affect the "high level" properties that are speed and power consumption. For example capacitance limits clock speed and also has an effect on power consumption, and leakage current reduces power efficiency. Capacitance and leakage current themselves depend on size. I think that the physical properties you mention (and maybe others) may be used to create a model, which can then be used to estimate clock speed and power consumption at different operating points.

Re: Intel Reinvents Transistors Using New 3-D Structure

#69

Post by daeken »

Symmetry wrote: post #61
daeken wrote: post #47

Earlier quoted context omitted.

They're closer together, but the distance traveled in total is the same. Imagine the transistors are pieces of paper, and you're drawing a line over them. If the paper is flat, then you're drawing a line of distance n , and the points are n apart. If you fold the ends of the paper together, then the points are 0 units apart (or near enough to make no matter), but that line still has a distance of n .

Oh, I think I get what your confusion is now. The signal doesn't have to travel up and over now any more than it did when everything was flat. The signal will travel up a few gate widths to the low resistance metal interconnect layers, travel a few tens or hundreds of gate widths sideways to get to the next transistor, then goes down again to make the connection. Going to 3D doesn't change this except to make the up…

Ah hah, I see what you're saying now. Thanks for clearing that up.
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