Earlier quoted context omitted.
One of the reasons Rosetta 2 works so well is Apple silicon sticks to the more restricted x86 memory model.
Does it? Apple's documentation seems to disagree [1]: "A weak memory ordering model, like the one in Apple silicon, gives the processor more flexibility to reorder memory instructions and improve performance, but doesn’t add implicit memory barriers." [1] https://developer.apple.com/documentation/apple_silicon/addr...
Here's a kernel extension someone built to manipulate this feature: https://github.com/saagarjha/TSOEnabler