Apple’s A14 Packs 134M Transistors/mm² • Hacker News Board

Re: Apple’s A14 Packs 134M Transistors/mm²

#21

Post by wincy » Tue, Oct 27, 2020, 8:33 PM UTC

tpowell wrote: post #16

I was curious just how many chips per wafer they net. From this 2018 article[1], it appears to be ~530 at 5nm, which would be $32ea if that yield is accurate. The same article estimated 7nm chips came out to $18ea. Apparently, R&D spend went up 50% from 7nm to 5nm. I'm curious to see how many flavors of the A14 Apple cooks up given the comparatively high die cost. [1] https://wccftech.com/apple-5nm-3nm-cost-transisto…

This might be one of the reasons they're transitioning to Apple Silicon, as it will allow them to justify the raising R&D costs over a wider array of products.

Re: Apple’s A14 Packs 134M Transistors/mm²

#22

Post by ineedasername » Tue, Oct 27, 2020, 8:34 PM UTC

What's the relative heat dissipation between logic & SRAM on a chip? The article talks about layering as a potential way forward for SRAM, but that would come with more complex TDP management, unless SRAM isn't burning watts at the same rate as the rest of the chip.

Re: Apple’s A14 Packs 134M Transistors/mm²

#23

Post by centimeter » Tue, Oct 27, 2020, 8:35 PM UTC

talentedcoin wrote: post #6

I think this is cool if they’re the future of the Mac, but aren’t these chips just wasted in the iPad? I say this as an iPad Pro (1st-gen) owner ... it’s already way more processing power than I can really use, because after trying for months to get a sensible workflow going (mostly based around Pythonista, Editorial and RealVNC) I’ve relegated it to a OneNote and Netflix machine. What’s the point other than the cool…

I bought my iPad Pro because it offered the smoothest RAW photo proofing process of any product I've used. A lot of this is obviously up to software as well as hardware, but still - the beefy processor is useful here.

Re: Apple’s A14 Packs 134M Transistors/mm²

#24

Post by ineedasername » Tue, Oct 27, 2020, 8:36 PM UTC

tpowell wrote: post #16

I was curious just how many chips per wafer they net. From this 2018 article[1], it appears to be ~530 at 5nm, which would be $32ea if that yield is accurate. The same article estimated 7nm chips came out to $18ea. Apparently, R&D spend went up 50% from 7nm to 5nm. I'm curious to see how many flavors of the A14 Apple cooks up given the comparatively high die cost. [1] https://wccftech.com/apple-5nm-3nm-cost-transisto…

I thought it was also interesting that cost-per-transistor had remained the same as well.

Re: Apple’s A14 Packs 134M Transistors/mm²

#25

Post by urthor » Tue, Oct 27, 2020, 8:37 PM UTC

talentedcoin wrote: post #6

I think this is cool if they’re the future of the Mac, but aren’t these chips just wasted in the iPad? I say this as an iPad Pro (1st-gen) owner ... it’s already way more processing power than I can really use, because after trying for months to get a sensible workflow going (mostly based around Pythonista, Editorial and RealVNC) I’ve relegated it to a OneNote and Netflix machine. What’s the point other than the cool…

Never underestimate the PUBG Mobile/Genshin Impact demographic basically.

There's a lot of corner cases there where certain consumers value it a lot.

Also performance per watt is a huge deal. The expanded power envelope that improved PPW brings allows 120hz displays which are battery hogs.

Re: Apple’s A14 Packs 134M Transistors/mm²

#26

Post by FullyFunctional » Tue, Oct 27, 2020, 8:39 PM UTC

rdw wrote: post #3

The article says that Apple isn't making full use of the 5nm process node, and blames lack of SRAM scaling for it (presumably due to the large amount of L3 cache). Is this a problem that all processors are about to hit, or is this going to be overcome once process engineers are more familiar with 5nm?

They optimize SRAM far in advance of introducing the process, after all this is one of the most critical components. It's very unlikely you'll see any further SRAM improvement on this process, but a process optimization can improve it (and everything else).

Re: Apple’s A14 Packs 134M Transistors/mm²

#27

Post by nimish » Tue, Oct 27, 2020, 8:39 PM UTC

This is about 35% denser than intel 10nm, and not a theoretical number.

Re: Apple’s A14 Packs 134M Transistors/mm²

#28

Post by baron816 » Tue, Oct 27, 2020, 8:40 PM UTC

Would hate to be the guy that had to count all those transistors.

Re: Apple’s A14 Packs 134M Transistors/mm²

#29

Post by moonchild » Tue, Oct 27, 2020, 8:41 PM UTC

topspin wrote: post #20

I really appreciate this analysis and the straightforward top line number 134e6/mm^2. The usual "node" figure is utterly meaningless; an electrical engineer couldn't care less about "feature" size (whatever that means.) What is the count of discrete components in a given area? There are 40 billion 5nm (the supposed "node" of these chips) squares in a millimeter of area. That's two orders of magnitude more dense than…

> The meaningful achievement is how many discrete electrical components are composed into a given area. Not some arbitrary dimension of some cherry picked subset of these components.

I disagree. The meaningful achievement is how power-efficient, fast, and cheap you can make a given chip. (Secondarily, how small and how durable wrt cosmic rays; but for most purposes these are not super important.)

If that follows as a result of many discrete electrical components being packed into a small area, great; but the latter isn't intrinsically interesting.

Re: Apple’s A14 Packs 134M Transistors/mm²

#30

Post by ineedasername » Tue, Oct 27, 2020, 8:42 PM UTC

callesgg wrote: post #15

jhloa2 wrote: post #4

Earlier quoted context omitted.

If SRAM is as ubiquitous throughout chip designs as the article suggests, wouldn't that mean the theoretical density prediction is off?

The theoretical maximum density is probably based on some type of physical law or just a simplified model. That is often what people talk about when they talk about theoretical maximums/minimums. Like if you have a box of dimensions 10x10x10cm the theoretical maximum number of dice of dimension 1x1x1cm you can fit in the box is 1000 dices. Chances are you won’t get 1000 dices in to the box as the world is more comple…

Which is why if you want to build a box that holds 1000 dice, you need to take into account the +/- tolerances in your build process. At a guess, you'd probably want to build at something like [dimensions] + 2*[tolerance]. So if your build process produced a 10cm cube with +/- 1mm, you'd want to build a 10.2mm cube so even a worse-case -1mm tolerance issue you'd still have +1mm of and so still be able to get the dice in without using force. And assuming the dice themselves didn't have some crazy high tolerance ranges.

I've got a side-gig/hobby making stuff, and the the 2x tolerance works pretty well as a rule of thumb for me, but the project type, material, and application probably play a big part in those considerations. Any industrial/mechanical/materials engineer care to weigh in?