Programming with RISC-V Vector Instructions
1–10 of 38 posts
Re: Programming with RISC-V Vector Instructions
#2Whoa, that's a well designed ISA.
Re: Programming with RISC-V Vector Instructions
#3Whoa, that's a well designed ISA.
Borrowed from the best.
Re: Programming with RISC-V Vector Instructions
#4Pretty cool. For RISC-V experts out there, can someone explain to me the purpose of the proxy kernel? I can't seem to wrap my head around it. Why not just run a normal kernel (e.g. Linux) on top of the emulator? What advantages/disadvantages does the proxy kernel have?
Re: Programming with RISC-V Vector Instructions
#5Re: Programming with RISC-V Vector Instructions
#6Pretty cool. For RISC-V experts out there, can someone explain to me the purpose of the proxy kernel? I can't seem to wrap my head around it. Why not just run a normal kernel (e.g. Linux) on top of the emulator? What advantages/disadvantages does the proxy kernel have?
It proxies most everything through HTIF to your host at the syscall layer so you just read(2), etc. to your host FS. It's also dead simple so you don't have to wait for it to boot really.
Re: Programming with RISC-V Vector Instructions
#7Earlier quoted context omitted.
Borrowed from the best.
For those of us not in the know, from whom were they borrowed?
The RISC-V Vector ISA is credited to Cray "vector processors" [1], explicitly by the RISC-V authors.
Additionally, I believe experimenting with vector ISAs was mentioned as one of the reasons they started another RISC research project, which ended up being RISC-V.
Re: Programming with RISC-V Vector Instructions
#8Earlier quoted context omitted.
For those of us not in the know, from whom were they borrowed?
The RISC-V Vector ISA is credited to Cray "vector processors" [1], explicitly by the RISC-V authors. Additionally, I believe experimenting with vector ISAs was mentioned as one of the reasons they started another RISC research project, which ended up being RISC-V. [1] https://en.wikipedia.org/wiki/Vector_processor
Yeah, RISC should have been called CISC, Cray Instruction Set Computer.
Re: Programming with RISC-V Vector Instructions
#9I highly recommend Lex Fridman's recent podcast with David Patterson [1] for anyone interested in learning about the history of RISC, computer architecture, and also interesting predictions re: Moore's Law.
Re: Programming with RISC-V Vector Instructions
#10Pretty cool. For RISC-V experts out there, can someone explain to me the purpose of the proxy kernel? I can't seem to wrap my head around it. Why not just run a normal kernel (e.g. Linux) on top of the emulator? What advantages/disadvantages does the proxy kernel have?
It gives you a hardware testing environment with system calls for reasonable amounts of wall clock time.
If you're simulating actual hardware, e.g., a Verilog description of a RISC-V microprocessor compiled to a cycle-accurate simulation with Verilator, your simulation rate is going to be ~10KHz. You can write useful tests with the Proxy Kernel (or something like it) that run in ~1 million instructions (minutes of wall clock time) while still getting full system calls like printf. However, booting Linux is out of the question (days of wall clock time). Running bare metal is useful, too, but you don't have system calls there.
If you're doing fast RISC-V virtualization, like on QEMU, or doing emulation on an FPGA, you're running at >1MHz and running a "normal kernel" like Linux is totally tractable. However, it would be foolhardy to expect to jump from hardware design to immediately booting Linux.