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Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

logic.ly

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Re: Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

#12

Earlier quoted context omitted.

(Disclosure: I wrote the simulation engine behind CircuitLab, a mixed-mode [i.e. analog+digital combined] circuit simulation engine.) Writing software to do digital logic simulation is quite simple. Everything is event-driven: if a signal "A" changes from 0->1 at time t_0, and this signal is an input to some gate "X", then at time t_0 + t_p (propagation delay) the output of that gate will update with the new value, a…

What do you do if the propagation delays are unknown or not constant (e.g., due to manufacturing process variations)?

Real digital logic is usually clocked at a rate which is slow enough for propagation and other effects to settle AND/OR for chip design, parts are speed binned after manufacture.

The principle is the same - you drop the clock rate until the circuit works reliably. You can usually do some ballpark estimates while designing - e.g. a small board full of TTL will usually be happy clocked at 10% of the theoretical maximum, it may work at 25%, 50% is optimistic unless the circuit is trivial, and 100% is only possible for a single gate or two if the board design is also fast enough.

Occasionally you'll see non-clocked designs, but they're much harder to model at speed because everything turns into a monostable, and each monostable will have a time tolerance. This is a bad thing from a design and reliability POV.

It's the same principle at the pro level, with the difference that you have multi-layer boards and much faster clock rates. The board routing uses some tricks to minimise propagation, switching transients, and transmission line reflections, but mostly there's incredibly advanced engineering and modelling involved in making a small-ish board that works reliably at GHz rates - certainly more complex than trying to guesstimate propagation using a very simple delay model.

Re: Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

#15

Earlier quoted context omitted.

What do you do if the propagation delays are unknown or not constant (e.g., due to manufacturing process variations)?

Real digital logic is usually clocked at a rate which is slow enough for propagation and other effects to settle AND/OR for chip design, parts are speed binned after manufacture. The principle is the same - you drop the clock rate until the circuit works reliably. You can usually do some ballpark estimates while designing - e.g. a small board full of TTL will usually be happy clocked at 10% of the theoretical maximum…

Thank you for your answer. Since non-clocked designs are hard to model and clocked designs at high rates are also hard to model, is there ever a crossover point in hardness (e.g., when they exceed a a certain number of components or physical size) or are clocked designs always considered asymptotically easier? On a related note, does the competitive advantage of one hardware manufacturer over another reduce primarily to a matter of which one has better circuit simulation and routing software?

Re: Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

#16
Cool. My favourite class in University went from low level, transistors, to gates to assembly. We used logisim and programmed our logic to an FPGA board. Final logic lab was building the circuit for a processor with two instructions of your choice and registers.

Re: Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

#17
I used logic.ly for a class last semester, we used it for about a month and built up to a very basic cpu. I found it pretty easy to pick up and fun to work in. Wouldn't be surprised if a lot of online computer arch classes use this in the coming online semester.

Re: Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

#18

Earlier quoted context omitted.

Real digital logic is usually clocked at a rate which is slow enough for propagation and other effects to settle AND/OR for chip design, parts are speed binned after manufacture. The principle is the same - you drop the clock rate until the circuit works reliably. You can usually do some ballpark estimates while designing - e.g. a small board full of TTL will usually be happy clocked at 10% of the theoretical maximum…

Thank you for your answer. Since non-clocked designs are hard to model and clocked designs at high rates are also hard to model, is there ever a crossover point in hardness (e.g., when they exceed a a certain number of components or physical size) or are clocked designs always considered asymptotically easier? On a related note, does the competitive advantage of one hardware manufacturer over another reduce primarily…

I have just a basic understanding but for example in a serial to digital converter they will use a base clock and a phase delayed clock signals to capture multiple samples in one base clock cycle time instead of just cranking up the base clock frequency.

Re: Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

#19
If this is sort thing looks fun, but you would want more of a game then one unique gaming company builds games where you create "fantasy circuits".

In TIS-100 you write assembly code for an unusual 12-node interconnected machine.

In the Shenzen I/O you write code to interface with pretend hardware, again with highly limited programming space but quite more accessible than TIS-100: https://store.steampowered.com/app/504210/SHENZHEN_IO/

An interesting twist is that most of the game manual is pretend hardware datasheets.

Hey, Zachtronics should do Microservices: The Game next.

Re: Logic.ly – Digital logic simulator for teaching logic gates and digital circuits

#20
post #7

In a similar vein, NandGame ( http://nandgame.com/ ) is an online game where the challenge is to progressively build a microprocessor, starting from simple logic gates. Show HN thread from a couple of years ago: https://news.ycombinator.com/item?id=17508151

I really liked https://asteriskman7.github.io/dldtg/

Its a cookie clicker type game mixed with an almost VHDL like circuit design language.

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