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Or the dozens of other devices in your house that have the benefit of mains voltage. I don't think perf per watt was a differentiator in the compute chosen for your TV, your monitor, your AV receiver, your fridge, etc.
Yes, but none of these things use significant compute.
And it's not unheard of for them to have FPGAs for that reason.
For folks writing in SpinalHDL, is anyone using Quartus? Or are you using a fully open-source toolchain? i.e. What is your workflow?
I'm interested in trying out SpinalHDL, but I'm not sure how to integrate it into what I'm doing.
Earlier quoted context omitted.
Yes, but none of these things use significant compute.
Monitors and TVs absolutely do. And it's not unheard of for them to have FPGAs for that reason.
This project looks amazing. For folks writing in SpinalHDL, is anyone using Quartus? Or are you using a fully open-source toolchain? i.e. What is your workflow? I'm interested in trying out SpinalHDL, but I'm not sure how to integrate it into what I'm doing.
This project is an FPGA based ray-tracer that uses Xilinx ISE written in SpinalHDL: https://github.com/tomverbeure/rt. This project uses SpinalHDL to drive an LED cube, which uses Quartus: https://github.com/tomverbeure/cube (it also uses a VexRiscv). And here is a small project that drives an LED matrix with WS2812B LEDs, that runs on an Upduino2 with a Lattice UP5K FPGA, which uses open source Yosys/NextPNR: https://github.com/tomverbeure/led_matrix.
This project looks amazing. For folks writing in SpinalHDL, is anyone using Quartus? Or are you using a fully open-source toolchain? i.e. What is your workflow? I'm interested in trying out SpinalHDL, but I'm not sure how to integrate it into what I'm doing.
I'm using SpinalHDL for all my hobby projects, and I use Intel Quartus, Xilinx ISE, or Yosys, depending on the FPGA family. This project is an FPGA based ray-tracer that uses Xilinx ISE written in SpinalHDL: https://github.com/tomverbeure/rt . This project uses SpinalHDL to drive an LED cube, which uses Quartus: https://github.com/tomverbeure/cube (it also uses a VexRiscv). And here is a small project that drives an…
It looks like a really nice abstraction. I've been working on the MiSTer project, writing arcade cores for the Cyclone V in VHDL.
I've made a huge effort to keep things clean, but SpinalHDL could be a great way to tame some of the code.
Will start blinking some LEDs and see how it goes...
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With the transition of compute from performance focussed to performance per watt focussed (due to cooling usually being the limiting factor), the niche for the FPGA has almost vanished. There are very very very few compute tasks where an FPGA solves a problem with better performance per watt than both a CPU and a GPU. I would bet that emulating a RISC-V program on x64 is far more power efficient than running a RISC-V…
An ECP5 will sit on the order of ~100mW and you can clock those up to dozens of MHz. They can have multiple cores running in parallel (an ECP5 85k will fit dozens, probably well over a hundred RISC-V cores if you do your homework.) Even a laptop sitting at 10W is going to be orders of magnitude more power inefficient than this in terms of raw instructions-per-cycle-per-watt if you're emulating. That is not the best m…
Worth mentioning SymbiFlow: https://symbiflow.github.io/ , it's a fully open-source flow for FPGAs, Xilinx support (targetting the Arty A7 that the project in this story uses for instance) is on the way so hopefully won't be long until you can build a opensource RISC-V SoC that can run Linux entirely on open source tooling.
To be clear, creating a linux capable Artix-7 image using only open source tools can be done today, right now! https://github.com/SymbiFlow/symbiflow-examples
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An ECP5 will sit on the order of ~100mW and you can clock those up to dozens of MHz. They can have multiple cores running in parallel (an ECP5 85k will fit dozens, probably well over a hundred RISC-V cores if you do your homework.) Even a laptop sitting at 10W is going to be orders of magnitude more power inefficient than this in terms of raw instructions-per-cycle-per-watt if you're emulating. That is not the best m…
Your comments will be much better without the condescending tone. I point this out because I also talk down to people unintentionally. It's a difficult habit to break.
I also researched the process of turning an SoC design into physical chips. I estimated the cost to be around USD $150,000 for the first handful of chips, using TSMC's CyberShuttle.
The learning curve for this technology is extremely steep. I would probably need to spend years learning the various skills.
The PolarFire SoC block diagram [1] shows a DRAM controller and a DRAM PHY.
The Arty A7 Reference Manual [2] talks about using the Xilinx Vivado to add peripheral blocks into the SoC design. Is this a way to add Xilinx's proprietary DRAM controller block, which would then need to be licensed separately?
Does Antmicro's demo use LiteDRAM to interface with Arty A7's DRAM PHY?
What would be involved in modifying VexRiscv and its MMU to support normal data memory and a separate read-only instruction memory? For someone with the necessary skills, is it a 1-month project or a 1-year project?
I checked a bunch of FPGA development boards. The only boards I found with multiple DRAM chips have the Cyclone V FPGA and cost >$1,000. Why do those boards cost so much more than the $150 Artix 7 boards?
[1]: https://www.microsemi.com/product-directory/soc-fpgas/5498-p...
[2]: https://reference.digilentinc.com/reference/programmable-log...
As cool as this is, enough with the FPGAs and the RISC-V Arduino clones. A real, relatively inexpensive (e.g. sub $100) RISC-V SoM/board that can run Linux is desperately needed (with at least at BeagleBone Black performance levels). I really like the idea of RISC-V and I'm willing to make the investment in software (and in fact have done so with QEMU), I just can't get any real hardware (for a non-silly price).
Once that exists, I think we'll see companies develop RISC-V chips cheap enough for low-end smartphones and other IoT devices. Those are the chips that are cheap enough to put in a <$100 board.