Nvidia CEO Introduces Nvidia Ampere Architecture, Nvidia A100 GPU

Post by evanb » Thu, May 14, 2020, 2:35 PM UTC

barbegal wrote: post #30

krapht wrote: post #13

Earlier quoted context omitted.

Physics simulations. There's a rule of thumb that to get an n-bit accurate result after a long chain of calculations, intermediate results should be stored with 2n bits. Often using the full dynamic range of a float is necessary because the magnitude of different physical phenomena varies so wildly. I guess people do store intermediate results in floats in order to take advantage of GPU acceleration. However, once yo…

I've always argued that if you are getting close to having to worry about underflow, overflow etc. then you have an ill-conditioned problem and just increasing the size of your intermediate results won't help you a huge amount because you need more precision from your inputs. There are very few fields where you need more than the 7 decimal digits afforded by floats. Maybe the only exceptions are in astrophysics.

Post by __alexs » Thu, May 14, 2020, 2:44 PM UTC

notact wrote: post #50

reedwolf wrote: post #26

Stealing Epic Games/Unreal Engine's thunder. If Nvidia was a human, they'd be the type to propose at someone else's wedding.

So wait, the GTC keynote which was scheduled weeks/months ago, happens to follow news that Epic dropped with absolutely no warning, and apparently that counts as stealing thunder. Is that really what you are saying?

Post by epmaybe » Thu, May 14, 2020, 2:47 PM UTC

ethbro wrote: post #33

In my experience, Jensen Huang's keynotes are unprofessional in the best possible way. I remember thinking during an entire GTC presentation "Wait, this guy is the CEO?" He seemed like an excited engineer who happened to stumble onto stage.

Post by BobbyJo » Thu, May 14, 2020, 2:49 PM UTC

tylerhou wrote: post #15

drewg123 wrote: post #10

I'm confused. Is there any relationship between the recent Ampere Arm64 servers ( https://news.ycombinator.com/item?id=22475036 ) and Nvidia's "Ampere Architecture", or is it just a case of them using the same name?

Same name, but Ampere the company probably came first (2017). They're both named after the famous mathematician and physicist. https://en.wikipedia.org/wiki/Andr%C3%A9-Marie_Amp%C3%A8re

Post by ethbro » Thu, May 14, 2020, 2:50 PM UTC

bitL wrote: post #60

ethbro wrote: post #47

Earlier quoted context omitted.

Hypothetically, from an ISA perspective, why couldn't Intel and AMD extend x86-64 more fully with SIMD / MIMD instructions? (as in, way more fully than MMX / SSE / AVX) Naive question, because I literally don't know the link between CPU instruction stream and GPGPU instruction stream. But it seems like there would be an opportunity to seize the higher (open) ground at the ISA level, and then force Nvidia to implement…

> why couldn't Intel and AMD extend x86-64 more fully with SIMD / MIMD instructions I think there is that latency vs bandwidth trade-off where CPU likes lower latency and GPU higher bandwidth, but you can't achieve the same with a single chip.