Earlier quoted context omitted.
And neither can be used as a compilation target for, say, Firefox, (or simpler, nethack) can they ?
Analog Devices provides a C/C++ compiler and a RTOS for SHARC, so I wouldn't be surprised if nethack could be compiled for the SHARC VLIW architecture (and its two branch delay slots).
Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
81–90 of 95 posts
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#82Earlier quoted context omitted.
> they baked implementation details into the ISA and became problematic when the implementation details changed. Same reason why stuff like VLIW has failed to catch on. These things are so dependent on specific hardware implementation details that one can hardly call them general-purpose ISA's anymore.
Moderns GPUs are VLIW machines.
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#83Earlier quoted context omitted.
A number of others you might encounter in your embedded devices: 68k, AVR, Z80. (CISC, RISC, CISC, if you’re curious.)
There’s (sadly) not that much 68k left these days, is there? Do you know of any specific companies still using them? (maybe ones that are hiring? :)
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#84Earlier quoted context omitted.
> There's nothing much that's CISC-like about ARM, I struggle to think that ARM can really be called reduced-instruction after neon or so.
RISC has never been about reduced number of instructions, but their complexity. A SIMD extension built around load/store architecture is quite compatible with the principles of RISC, despite the fact that such an extension might have very numerous instructions.
> The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[23] In particular, RISC processors typically have separate instructions for I/O and data processing.
So yeah, if SIMD instructions can execute in a single cycle (or maybe even a small number), then it still counts.
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#85ARM and RISC-V have collectively removed any remaining niches (or future prospects) for MIPS.
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#86Earlier quoted context omitted.
And ported to DEC Alpha too! It's one of my weirdly favorite ports of NT just because of how little use I believe it ever actually got.
I've seen live Alpha installations of windows NT driving RIPs at large format printing shops in the 90s. It was also not unheard of at VMS shops.
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#87The writing's been on the wall for MIPS for ages. AFAIK it's not better than ARM in any meaningful way.
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#88I don't think MIPS is going to completely disappear as long as Linux works on it. Someone somewhere in some country will keep making them as long as the licensing situation is more favorable for whatever use than ARM or x86. If the owning company is going bankrupt that means making MIPS CPUs will be cheaper than ARM or x86.
In China they have lots of new MIPS developments based on existing MIPS architecture. The question it's not if someone will use some old MIPS ISA in a few years from now on, the question is if someone will improve the ISA from now on, in the same way x86 and ARM are consistently being improved. Some companies are still fabbing old Z80 CPUs, but that's not to say Z80 has a bright future.
CIP-United still promises to provide enhanced versions of the both the architecture and the MIPS Warrior cores for the Chinese market, regardless of what happens to MIPS Technologies. This may seem utterly futile now, but it is also the very thing that the US Committee on Foreign Investment was trying to prevent when it required MIPS to be spun out of Imagination Technologies when that got sold to Chinese investors.
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#89The writing's been on the wall for MIPS for ages. AFAIK it's not better than ARM in any meaningful way.
The creator of ARM speaks well of RISC-V and considers ARM yesterday's old news and has moved on. Comparing MIPS to ARM in essentials of architecture is MIPS more beautiful? ARM I understand is a mess that has evolved for its niche.
The old 32-bit Arm (now called Aarch32) was quite different and only somewhat RISC-like. Arm's Aarch64 however is mostly derived from MIPS64 with a lot of modernization plus some parts (exception levels) from 32-bit Arm.
MIPSr6 was an attempt of modernizing MIPSr5 by removing all the ugly bits (delay slots!) but the incompatible instruction encoding prevented it from being widely adopted. You cannot buy a single MIPSr6 machine that a mainline Linux runs on.
RISC-V's design looked at all RISC architectures (Berkely RISC, MIPS, SPARC, Power, Arm, ...) for inspiration and took the best parts of each. Leaving out all the historic baggage means it's simpler (the manual is a fraction of the size), but most of the important decisions are the same as in MIPSr6 and Armv8/Aarch64.
One notable difference is the handling of compressed (16-bit) instructions: ARMv8/Aarch64 doesn't have them at all (like RISC-I/RISC-II, ARMv3 and MIPS-V), MIPSr6/microMIPS needs to switch between formats (like ARMv4T through ARMv6) and in RISC-V they are optional but can be freely mixed (somewhat like ARMv7 and nanoMIPS).
Re: Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More
#90Earlier quoted context omitted.
> There's nothing much that's CISC-like about ARM, I struggle to think that ARM can really be called reduced-instruction after neon or so.
Why? NEON operates on registers, so the load-store principle is still fully in effect. And it maps directly to special-purpose hardware.
- Predication as a major architectural feature -- every instruction can be conditionally executed - Complex load-store instructions: ldm/stm can operate on a large set of registers in a single instruction, including performing a branch by loading into the instruction pointer - 16-bit Thumb instruction format (also optionally present in RISC-V and newer MIPS)
64-bit Arm mostly drops all of the above and is basically a traditional RISC implementation.