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A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

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21–30 of 93 posts

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#21

Once I worked at a place which was very interested in protecting the IP inherent in their firmware. They gave me a research assignment to get an idea of how difficult it would be for an attacker to extract it as a binary given unlimited physical access to a sample device. Since I read and write Chinese, I did some searching on Chinese-language sites and found a company advertising their ability to do just that... for…

I wonder if classic chip-off methods would work (they no longer work on mobile devices due to encryption advances)

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#22

Earlier quoted context omitted.

If the FPGA can be updated, attacker can take over the hardware and reprogram it. If attacker gets access to the bitstream, the has complete control over the FPGA.

But if an attacker is already "inside" your system and is able to access the interface for configuring the FPGA, I think you have already lost...

He bought the FPGA, modified it, and sold you a compromised one.

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#23

While this does open up the code (sans descriptive text) to external attacks, I rather feel that once you have a logic analyzer or compromised microcontroller on the logic bus of your secure device you've got the attacker on the wrong side of the airtight hatchway. I'm personally much more interested in what it means for 'attackers' who wish to use it to open up their own hardware. Perhaps that might not align with t…

Attacker needs physical access to just one device in the whole product line that uses the same encryption key.

After that, all you need is to get the device to update using the bitstream you made. In some cases this could be remote attack.

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#24

Earlier quoted context omitted.

If the FPGA can be updated, attacker can take over the hardware and reprogram it. If attacker gets access to the bitstream, the has complete control over the FPGA.

But if an attacker is already "inside" your system and is able to access the interface for configuring the FPGA, I think you have already lost...

Attacker needs physical access to just one device in the whole product line that uses the same encryption key.

After that, all you need is to get the device to update using the bitstream you made.

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#25
post #17

>3.5 Wrap-Up: What Went Wrong? >These two attacks show again that nowadays, cryptographic primitives hold their security assumptions, but their embedding in a real-world protocol is often a pitfall. Two issues lead to the success of our attacks: First, the decrypted data are interpreted by the configuration logic before the HMAC validates them. Generally, a malicious bitstream crafted by the attacker is checked at th…

This is another example of what Moxie Marlinspike calls the "cryptographic doom principle". If you do anything, anything with a ciphertext before checking authenticity, doom is inevitable.

For others following along: https://moxie.org/blog/the-cryptographic-doom-principle/ (2011)

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#26
post #18

Earlier quoted context omitted.

Yes. Unfortunately, it's a double-edged sword. The same technology is needed for the FOSS community to create secure hardware.

Security through obscurity? Nah.

This was security through a cryptographic design. It was just a broken design. If you consider confidential symmetric or privkeys "obscurity," sure, all crypto is obscurity.

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#27

So can I use this hack to use open source tools on these FPGAs?

No. It means people will be able to copy FPGA's like was possible in the 2000's. It also means that the design in an FPGA could be altered by an unauthorized 3rd party without having to physically replace the device.

Some FPGA's require bitstream encryption. On those devices, breaking this encryption is the first of many steps to making an opensource toolchain

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#28

While this does open up the code (sans descriptive text) to external attacks, I rather feel that once you have a logic analyzer or compromised microcontroller on the logic bus of your secure device you've got the attacker on the wrong side of the airtight hatchway. I'm personally much more interested in what it means for 'attackers' who wish to use it to open up their own hardware. Perhaps that might not align with t…

Attacker needs physical access to just one device in the whole product line that uses the same encryption key. After that, all you need is to get the device to update using the bitstream you made. In some cases this could be remote attack.

I'm not sure this is true. This attack allows reading the encrypted bitstream, but it doesn't say anything about allowing you to sign modified bitstreams.

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#29
post #4

This is not small issue. Up to 10% of FPGA's in the market can be affected. RAID-, SATA-, NIC- controllers, Industrial control systems, mobile base stations, data centers, devices like encrypted USB sticks and HDD's. In some cases it's possible to carry the attack remotely.

Only ones who need to keep firmwares secret will be affected. There are few companies I knew who transitioned from MCUs to FPGAs solely for their obsession of keeping their "IP" from leaking, hoping that FPGA will provide more obscuration than simple encrypted MCU firmware.

Bitstream is not firmware. It’s gate configuration.

It’s not a pedantic difference. It’s much harder to reverse hardware configuration back to human readable logic like Verilog.

“Bitstream is not firmware” is the first thing you learn when working with FPGAs.

Re: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

#30
The number of people glossing over his to take a bitstream which is the gate configuration of the fabric and read it back to human logic like Verilog is extremely few people and always a lot of time.

This is a big issue for cloning though.

Oh AES CBC, when will you stop disappointing!?

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