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CacheOut: Leaking Data on Intel CPUs via Cache Evictions

cacheoutattack.com

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Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#51
post #37

Again, I reiterate: it's not humanly possible to make performant, general purpose CPU that is 100% safe from instruction level attacks. Untrusted code execution must go, that's the only way. The genie is out of the bottle now. There will be more and more practical instruction level attacks with each year now.

You can avoid instruction-level attacks by putting untrusted code on an isolated core with an isolated memory module, right? That seems more likely to me than everyone disabling javascript.

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#52
post #4
post #2

Did AMD design their processors with these side channel attacks in mind, or is it a matter of where the security research is focused?

> AMD is not affected by CacheOut, as AMD does not offer any feature akin to Intel TSX on their current offering of CPUs. It seems to be down to the notoriously buggy TSX (hardware transactional memory) in Intel CPUs.

It's interesting that TSX seems to be one of those holy grails that causes more problems than it solves - trying to implement TSX caused, I believe, huge problems for Sunacle's Rock processor team.

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#53
post #37

Again, I reiterate: it's not humanly possible to make performant, general purpose CPU that is 100% safe from instruction level attacks. Untrusted code execution must go, that's the only way. The genie is out of the bottle now. There will be more and more practical instruction level attacks with each year now.

I don’t think so. Side channel attacks became recently more mainstream and people start designing stuff with it in mind. What you see here is yet another attack on a relatively unused Intel-only x86 extension. The bigger problem is that Unixes and Windows are pretty bad at sandboxing syscalls by default.

I do remember there 100% were academic papers throwing barbs into Pentium 3 branch predictor security back in nineties. They just went unnoticed for there being no Google logo on the paper.

People in hardware engineering community knew of their existence long ago. It was just them not being practically exploitable that kept them from headlines.

But now we have a multibillion buck virtualised hosting industry, and JS with JIT in every browser — a million buck incentive for black hats to poke into architectural vulnurabilities

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#54
post #37

Again, I reiterate: it's not humanly possible to make performant, general purpose CPU that is 100% safe from instruction level attacks. Untrusted code execution must go, that's the only way. The genie is out of the bottle now. There will be more and more practical instruction level attacks with each year now.

You can avoid instruction-level attacks by putting untrusted code on an isolated core with an isolated memory module, right? That seems more likely to me than everyone disabling javascript.

Maybe with the recent influx of larger core count systems, this isn't entirely unreasonable in the future.

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#55
post #37

Again, I reiterate: it's not humanly possible to make performant, general purpose CPU that is 100% safe from instruction level attacks. Untrusted code execution must go, that's the only way. The genie is out of the bottle now. There will be more and more practical instruction level attacks with each year now.

You can avoid instruction-level attacks by putting untrusted code on an isolated core with an isolated memory module, right? That seems more likely to me than everyone disabling javascript.

> You can avoid instruction-level attacks by putting untrusted code on an isolated core with an isolated memory module, right?

No, unfortunately. Side channels will work even across numa domains, and cores with own memory.

Side channel free hardware is extremely hard to do even in simplest ISAs specially made for that. Look at how credit card industry keeps struggling making safe smartcards.

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#56
post #47

Earlier quoted context omitted.

> Untrusted code execution must go, that's the only way. This is how you get corporate rule over what can and can't run on machines you own. Safer architectures can be developed, without handing over control to a third party.

I don't believe that even a complete comparch-101 in-order, non-pipelined, architecture without branch prediction, and register renaming can be made safe enough. But yes, the industry made an extremely risky bet a decade ago with both virtualisation, and running unsafe Javascript with JIT. It will take many billions for the industry to do a U-turn, and switch back to dedicated servers as a golden standard, and puttin…

> I don't believe that even a complete comparch-101 in-order, non-pipelined, architecture without branch prediction, and register renaming can be made safe enough.

Disagree. You do have to put a lot of work into the process. Formal spec as well as a formal method/simulation. There are certainly a lot of fun things to consider in that, but I don't think it's completely unfeasible.

As an aside, one of the things that intrigues me about RISC-V is things such as a formal instruction set spec being openly published [1]. You could apply all sorts of tooling to that before actually creating silicon.

> But yes, the industry made an extremely risky bet a decade ago with both virtualisation, and running unsafe Javascript with JIT.

Focusing so much on Jitting JS was as bad idea then just like it was now. The entire world of the web is artificially propped up and will probably die the way it should have died when it started: with people frustrated by constant security vulnerabilities enabled by a group of ad companies who don't care about anything but money.

> It will take many billions for the industry to do a U-turn, and switch back to dedicated servers as a golden standard, and putting a leash on ambitions of browser makers.

WRT Dedicated servers, if anything the industry needs that push now anyway. I've yet to see a 'Real' cost projection on a SaaS 'rewrite'; i.e. if the current thing has been in use 5 years longer than it should have, your cost models should go out 5 years longer than you intend your new solution to exist.

Which would be ironic; my pain is in the beancounting side (usually what an org really cares about) yet security will be the more likely scenario.

I think the cat is out of the bag for the browser market though. Users have on the whole gotten 're-enclosed' thanks to modern laptops tending towards small eMMC or SSD sizes.

But FFS, this sort of thing is the reason WASM scares the daylights out of me.

[1] https://github.com/mrLSD/riscv-fs

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#57
post #9
post #2

Did AMD design their processors with these side channel attacks in mind, or is it a matter of where the security research is focused?

Mostly, it seems to be a difference in design philosphy - AMD processors prevent speculative reads of data that shouldn't be accessible almost everywhere, whereas Intel ones allow them pretty much everywhere. This particular attack requires TSX which AMD processors don't have, but I don't think it'd work on AMD processors anyway because they're not missing the security check that Intel ones are. If I remember rightly…

"Faster than possible" seems really appropriate here.

They built a bunch of tech debt into their processors to boost their numbers, and now they hens are coming home to roost.

What I'm wondering is how many changes this will make to their product roadmap, and to what degree it will make next generation chips look lackluster compared to what people (think they) have now.

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#58
post #47

Earlier quoted context omitted.

I don't believe that even a complete comparch-101 in-order, non-pipelined, architecture without branch prediction, and register renaming can be made safe enough. But yes, the industry made an extremely risky bet a decade ago with both virtualisation, and running unsafe Javascript with JIT. It will take many billions for the industry to do a U-turn, and switch back to dedicated servers as a golden standard, and puttin…

> I don't believe that even a complete comparch-101 in-order, non-pipelined, architecture without branch prediction, and register renaming can be made safe enough. Disagree. You do have to put a lot of work into the process. Formal spec as well as a formal method/simulation. There are certainly a lot of fun things to consider in that, but I don't think it's completely unfeasible. As an aside, one of the things that i…

Can't edit, but obviously the web won't die. But it is going to change a bit over the next few years still; the privacy changes are likely to be a big catalyst for a lot of change...

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#59
post #37

Again, I reiterate: it's not humanly possible to make performant, general purpose CPU that is 100% safe from instruction level attacks. Untrusted code execution must go, that's the only way. The genie is out of the bottle now. There will be more and more practical instruction level attacks with each year now.

>Untrusted code execution must go, that's the only way.

Ironically, you have to enable third party javascript to even view the page.

Re: CacheOut: Leaking Data on Intel CPUs via Cache Evictions

#60
post #31
post #20

Earlier quoted context omitted.

It is known since... forever?, that one should not speculate across security boundaries. This was not enough to avoid Spectre, but this was largely enough to avoid TONS of security vulns Intel is also susceptible to. Somebody messed-up big time. Or from a business point of view did they? Intel current problems are manufacturing and the continuously lower power of their "legacy" processor (except due to manufacturing…

>It is known since... forever?, that one should not speculate across security boundaries. ... if you value security over raw performance. Clearly Intel has decided at some point that it was worth playing with fire in order to get ahead in benchmarks. In their defence it seems to have worked reasonably well for them for quite a while. >The people most annoyed are the users. I wish, but I wonder how much of that is tru…

For most of Intel’s existence people ran fairly trusted workloads side-by-side. It wasn’t until “the cloud” that things really changed.
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