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Reviewing Bad Schematics as EE Interview Tactic

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Re: Reviewing Bad Schematics as EE Interview Tactic

#101

Post by kragen »

cushychicken wrote: post #97
kragen wrote: post #77

Earlier quoted context omitted.

It's pretty bizarre, you have to admit, for junior EEs not to know this — isn't it?

The more I think about it, no - it's not. For one thing, many of my professors (in fact, probably all of them) were very theory focused, and had very little experience implementing electronics. I think they figured that practical topics like this were too specific to lecture about, and we'd pick it up on the job anyway. I'd have to assume that mindset is not wholly exclusive to my undergraduate degree. For another th…

Well, I've definitely taken a pre-EE class where we breadboarded a bunch of logic circuits without decoupling caps. But #electronics on Freenode, Horowitz & Hill, and EEVblog are all pretty emphatic about them, so I figured everybody would know by the time they considered themselves a junior EE.

Re: Reviewing Bad Schematics as EE Interview Tactic

#102

Post by Sanzig »

mlyle wrote: post #39
userbinator wrote: post #17

Earlier quoted context omitted.

The closest standard value for that resistor would be a 3k3, if I'm not mistaken... In the software industry we have a similar problem; alot of people can follow instructions on how to glue together lots of libraries and frameworks, but have no idea how to go beyond that --- or understanding of how computers work in general --- much less debug it when something goes wrong. There's a classic article about this: https:…

Yah, but IMO 1mA is on the "low end" of lit, so you want to round down the resistor value to get a little more current. Pick 2k7 instead. Most small LEDs will tolerate per datasheet 20mA; 4mA is "well-lit". A little less than 1mA is going to be pretty anemic looking on lots of LEDs. So I'd be more inclined to put down 470 to 1k5.

If it's just a bare LED on a board (ie: not in a case going through a light pipe or diffuser), 1 mA is actually pretty bright with modern LEDs. They're a lot more efficient than they used to be.

For use as indicators for firmware debugging under typical office lighting, I find 1 mA to be the "sweet spot" - bright enough that I can tell it's lit with a quick glance, but not so bright that if I'm staring at the board it becomes uncomfortable to look at, or distracting out of the corner of my vision.

However, if it's for indication for an operator of a device, and it's inside a case going through some lossy elements (eg: aforementioned light pipe or diffuser), I'll definitely use more current to make it a bit brighter.

Re: Reviewing Bad Schematics as EE Interview Tactic

#103

Post by mlyle »

Sanzig wrote: post #102
mlyle wrote: post #39

Earlier quoted context omitted.

Yah, but IMO 1mA is on the "low end" of lit, so you want to round down the resistor value to get a little more current. Pick 2k7 instead. Most small LEDs will tolerate per datasheet 20mA; 4mA is "well-lit". A little less than 1mA is going to be pretty anemic looking on lots of LEDs. So I'd be more inclined to put down 470 to 1k5.

If it's just a bare LED on a board (ie: not in a case going through a light pipe or diffuser), 1 mA is actually pretty bright with modern LEDs. They're a lot more efficient than they used to be. For use as indicators for firmware debugging under typical office lighting, I find 1 mA to be the "sweet spot" - bright enough that I can tell it's lit with a quick glance, but not so bright that if I'm staring at the board i…

I can't be sure it's "on" unless it leaves little 0603-sized purple spots in my vision. ;)

(Maybe I'm biased because I often have my office window open and it's bright... and having couple orders of magnitude of current above what a microcontroller pullup/pulldown will source/sink has been nice sometimes-- that or I'm just stubbornly trying to justify following the very-old 4mA rule of thumb).

Re: Reviewing Bad Schematics as EE Interview Tactic

#104

Post by yummypaint »

cushychicken wrote: post #59
peter_d_sherman wrote: post #54

Excerpt: "Need some ideas for a crappy schematic? Here are some easy ones I can think up off the cuff: o Current limiting resistors missing (BJTs, diodes, etc.) o Shorting a potentiometer node to a rail o Voltage regulators missing capacitors at input/output o Missing pull-up/pull-down resistors on digital buses o Missing decoupling capacitors o Powering ADC reference voltages from a switching supply o Transistors pl…

I've never heard of a whole book, but I can see how it'd be a great book if someone really took the time to make it. I guess you could argue that The Art of Electronics kind of fills this niche. Horowitz and Hill call out a bunch of non-functional or error prone circuits with large, friendly "DON'T DO THIS" labels. The second edition had a great section at the end of each chapter entitled "Bad Circuits" that served j…

That's too bad they removed the bad circuits. I found those extremely useful when first starting out. Sometimes my first guess at how to do something was explicitly noted as a bad circuit, which i suspect was the intention. After reading about a new component, students often wonder "can i just do x instead?" and the bad circuits section did a great job of anticipating these kinds of questions.

Re: Reviewing Bad Schematics as EE Interview Tactic

#105

Post by jdsully »

mbell wrote: post #91
jdsully wrote: post #19

Earlier quoted context omitted.

Decoupling capacitors need to be within a few mm of the integrated circuit consuming the power. It really doesn't matter if the voltage regulator has them or not. This is different than for bulk capacitors, but even those should still be on the same PCB assembly because connectors have higher resistance and this will limit their ability to handle transient surges.

> It really doesn't matter if the voltage regulator has them or not. Not all LDOs are stable without external output capacitance in a particular range / ESR.

The point is the LDO's capacitance or lack there of has no bearing on whether decoupling capacitors are required.

Understanding that the capacitor and the trace form an RC circuit and that distance matters is what separates a professional from a beginner.

Re: Reviewing Bad Schematics as EE Interview Tactic

#106

Post by cushychicken »

kragen wrote: post #101
cushychicken wrote: post #97

Earlier quoted context omitted.

The more I think about it, no - it's not. For one thing, many of my professors (in fact, probably all of them) were very theory focused, and had very little experience implementing electronics. I think they figured that practical topics like this were too specific to lecture about, and we'd pick it up on the job anyway. I'd have to assume that mindset is not wholly exclusive to my undergraduate degree. For another th…

Well, I've definitely taken a pre-EE class where we breadboarded a bunch of logic circuits without decoupling caps. But #electronics on Freenode, Horowitz & Hill, and EEVblog are all pretty emphatic about them, so I figured everybody would know by the time they considered themselves a junior EE.

>I've definitely taken a pre-EE class where we breadboarded a bunch of logic circuits without decoupling caps

Same! I didn't realize you needed them until I entered industry. I think that's a little disappointing - it's a very simple explanation, just one that most professors don't choose to spend time on.

I'm trying to put together a good demonstration of why you need decoupling capacitors in a lab setting. Best one I can think of is paralleling a bunch of inverters with no decoupling caps, and then measuring the current draw on the rail using a shunt resistor.

Re: Reviewing Bad Schematics as EE Interview Tactic

#107

Post by mng2 »

PascLeRasc wrote: post #70
cushychicken wrote: post #64

Earlier quoted context omitted.

Sounds like the interviewer tried to use this tactic, and did a lousy job of applying it. 1) "Why it wouldn't work" is vague and nonspecific. "Applying power and hearing a pop/smelling smoke" is a big hint. You have to phrase the question in a way that gives up some information for it to be a decent use of time. 2) Complexity fucking kills these interviews. You shouldn't be handing off a multi-page schematic with com…

Ok, to be fair, they did say "when we turned it on, part of it blew up" when I asked for more details, and it was just a 2-page schematic with 6-7 subsections. I think it was pretty fair, I'm just frustrated that it felt like I couldn't solve it by thinking slowly and methodically. It was a really cool company and I'd have loved to work there. It's the kind of place where I want to be a good fit.

Did they tell you exactly where it blew up? Then it might be fair, 2 pages is not that big. Though you'd still be at quite a disadvantage compared to someone who spent a lot of time designing the thing.

I gotta say though, if they themselves designed this board that promptly blew up, perhaps they should recalibrate their expectations for EEs.

Re: Reviewing Bad Schematics as EE Interview Tactic

#108

Post by kragen »

cushychicken wrote: post #106
kragen wrote: post #101

Earlier quoted context omitted.

Well, I've definitely taken a pre-EE class where we breadboarded a bunch of logic circuits without decoupling caps. But #electronics on Freenode, Horowitz & Hill, and EEVblog are all pretty emphatic about them, so I figured everybody would know by the time they considered themselves a junior EE.

>I've definitely taken a pre-EE class where we breadboarded a bunch of logic circuits without decoupling caps Same! I didn't realize you needed them until I entered industry. I think that's a little disappointing - it's a very simple explanation, just one that most professors don't choose to spend time on. I'm trying to put together a good demonstration of why you need decoupling capacitors in a lab setting. Best one…

Breadboard parasitics don't help. Or, rather, they do.

Re: Reviewing Bad Schematics as EE Interview Tactic

#109

Post by cushychicken »

kragen wrote: post #108
cushychicken wrote: post #106

Earlier quoted context omitted.

>I've definitely taken a pre-EE class where we breadboarded a bunch of logic circuits without decoupling caps Same! I didn't realize you needed them until I entered industry. I think that's a little disappointing - it's a very simple explanation, just one that most professors don't choose to spend time on. I'm trying to put together a good demonstration of why you need decoupling capacitors in a lab setting. Best one…

Breadboard parasitics don't help. Or, rather, they do.

They help, until they don't. Or they don't until they do! XD

Re: Reviewing Bad Schematics as EE Interview Tactic

#110

Post by kragen »

cushychicken wrote: post #109
kragen wrote: post #108

Earlier quoted context omitted.

Breadboard parasitics don't help. Or, rather, they do.

They help, until they don't. Or they don't until they do! XD

Maybe you should involve an ADC or DAC in your demo. Shitty audio is a more convincing problem than a VCC current measurement, and even tens of mV of ground bounce should be quite audible.
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