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Reviewing Bad Schematics as EE Interview Tactic

cushychicken.github.io

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Re: Reviewing Bad Schematics as EE Interview Tactic

#71

Post by xref »

EdwardDiego wrote: post #61

We've used what we call the "Kobayashi Maru" coding exercise with developers. It was code deliberately filled with various errors, from JavaDoc with @param names not matching argument names, to generic issues, to more subtle issues. One of the last ones involved threading and concurrent access. It also had a test suite to help candidates gauge their progress for programmatic issues, not so helpful for code style issu…

I thought at least in TDD your tests could “never be wrong” since you have to write code that makes the tests pass, not vice versa

Re: Reviewing Bad Schematics as EE Interview Tactic

#72

Post by bboreham »

PascLeRasc wrote: post #51

I had one of these for an interview a few months ago. A huge schematic and I was told to find out "why it wouldn't work". It took me about 10 minutes to figure out that one FET's diode network was set up so that it'd short out and fail, and I ended up failing the interview for taking so long and labeling every subsection. They told me this was a spot test, and this kind of thing should just jump out immediately if yo…

I would suggest it’s not about “being smart enough”, but about pattern-matching. Over time, the brain gets trained to recognise things and react without conscious effort. You haven’t put in enough repetitions to get to that point yet, for that interview.

Re: Reviewing Bad Schematics as EE Interview Tactic

#73

Post by Gibbon1 »

PascLeRasc wrote: post #51

I had one of these for an interview a few months ago. A huge schematic and I was told to find out "why it wouldn't work". It took me about 10 minutes to figure out that one FET's diode network was set up so that it'd short out and fail, and I ended up failing the interview for taking so long and labeling every subsection. They told me this was a spot test, and this kind of thing should just jump out immediately if yo…

I started doing board level design and firmware in 1984. What's that now, 35 years? I'd rather have a methodical EE than smug cowboys like those guys.

They failed you for doing what any competent engineer would do.

Re: Reviewing Bad Schematics as EE Interview Tactic

#74

Post by kragen »

userbinator wrote: post #6
rightbyte wrote: post #3

Earlier quoted context omitted.

It seems strange that the author has not met a single one that understands that concept since it is quite basic. I am guessing he just is bad at interviewing and asks trick questions till he meet someone who know the interviewing game inside out. Examples he gives: "Current limiting resistors missing (BJTs, diodes, etc.) Shorting a potentiometer node to a rail Voltage regulators missing capacitors at input/output Mis…

how should you know that the voltage regulator doesn't have internal caps without seeing the specs? Can you name one voltage regulator that has them? Maybe you've worked with a few, but just off the top of my head, the 78xx, 317, and 1117 don't, and neither do all the other miscellaneous ones that I've seen in consumer electronics.

78xx/79xx don't need caps for stability either, according to their datasheets. Still seems a bit janky to leave them out.

Re: Reviewing Bad Schematics as EE Interview Tactic

#75

Post by kragen »

spatular wrote: post #20
rightbyte wrote: post #15

Earlier quoted context omitted.

I hate to maybe be proving his point by showing that I'm not into the EE field and thinking of a board mounted DCDC-converter as a voltage regulator (which it is but not what you usually call it in english?) I would still argue that logic IC have alot of internal pull ups. Or that eg. "Reset sequence of digital component is wrong" is a bad whiteboard question.

I believe that without qualification "linear regulator" could be just anything that regulate voltage. Usually you can easily tell from schematics around it if it's some switching IC, an LDO or a module. And if you have layout or 3d render of the board it'd be almost certain. Otherwise the person may just ask: "where are caps, or is this thing a module or what?"

No, switchers aren't “linear.” And on a schematic the regulator isn't going to be a box labeled “regulator”! It will have a part number, probably a familiar one.

Re: Reviewing Bad Schematics as EE Interview Tactic

#76

Post by kragen »

PascLeRasc wrote: post #52
userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

My EE education didn’t cover decoupling caps, and from talking to others from different schools they didn’t learn it either. It's something that only comes out in DIY projects, and unfortunately most schools don't care about projects or fostering independent/continuous learning.

It's in Horowitz & Hill. What was your introductory textbook?

Re: Reviewing Bad Schematics as EE Interview Tactic

#77

Post by kragen »

cushychicken wrote: post #55
userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

I didn't expect when I wrote this post that the decoupling caps comment would be the one that starts the HN flame thread. XD

It's pretty bizarre, you have to admit, for junior EEs not to know this — isn't it?

Re: Reviewing Bad Schematics as EE Interview Tactic

#78

Post by kragen »

madengr wrote: post #22

Here are some of my RF specific interview questions. Spend no more than 1 minute on each. Power Amplifiers Q: Where do GaAs/GaN FETs DC gate currents originate, and why are they positive and negative? Q: How would you temperature compensate the transistor DC bias. Q: What is AM-AM and AM-PM distortion and how would you measure it? Q: Give an example of a “memory effect”. Passive RF/Microwave Circuits Q: How would you…

These are for the most part considerably harder than noticing a backwards protection diode or a missing base resistor.

Re: Reviewing Bad Schematics as EE Interview Tactic

#79

Post by esmi »

userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

It’s not obvious that you need them. In modern hw especially, often you don’t. Most people add them because it is (usually) not harmful and it can be helpful and they don’t care if it’s wasteful. https://youtu.be/P8MpZGjwgR0

Re: Reviewing Bad Schematics as EE Interview Tactic

#80

Post by esmi »

PascLeRasc wrote: post #52
userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

My EE education didn’t cover decoupling caps, and from talking to others from different schools they didn’t learn it either. It's something that only comes out in DIY projects, and unfortunately most schools don't care about projects or fostering independent/continuous learning.

Are you an analog EE? If so that’s surprising. Did you have any microelectronics classes where you essentially build up your own opamp, one stage at a time? Bypassing is usually covered in this class, or in its lab, especially when discussing PSRR of the system.

Digital systems classes can cover it too, when going over power distribution, but that’s usually a graduate level class.

The digital VLSI or signal processing tracks of EE might not require this stuff anymore.

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