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Reviewing Bad Schematics as EE Interview Tactic

cushychicken.github.io

61–70 of 111 posts

Re: Reviewing Bad Schematics as EE Interview Tactic

#61
We've used what we call the "Kobayashi Maru" coding exercise with developers.

It was code deliberately filled with various errors, from JavaDoc with @param names not matching argument names, to generic issues, to more subtle issues. One of the last ones involved threading and concurrent access. It also had a test suite to help candidates gauge their progress for programmatic issues, not so helpful for code style issues (that JavaDoc comment).

Basically, we wanted to see the dev a) look at the reds and yellows in their IDE, b) run the tests, and then c) prioritise the issues. And d) say "these tests are wrong"

It was a highly effective filter for people with "qualifications" from dubious private training institutes (one candidate fixated on the red Javadoc for a mismatched parameter name, we hinted that he check the arguments in the method, he muttered "method, method, method..." to himself while scrolling down the code looking for the actual word 'method' - spoiler, he didn't find it, and he didn't get the job), but we left it behind when we found it was causing candidates genuine anxiety when they couldn't get all the tests to pass - which was intentional - anyone who figured out that the tests were deliberately wrong was an instant hire.

But we felt it was unfair, it's very very hard in a job interview to say "hey, I think your tests are wrong" so we dropped it.

These days, we use a simple filter - write code in your preferred language to find the element in the list that only has one occurrence. It's surprisingly effective as a first pass. People with years of Scala on their resume from writing Spark jobs, who choose Scala, but who can't quite get the hang of how you define an array of X in Scala... when you find yourself telling them to use square brackets for generics instead of angle brackets, you learn a lot about their actual capabilities vs. their projected.

Re: Reviewing Bad Schematics as EE Interview Tactic

#62
I only have a basic level of understanding of EE stuff, but I've been interviewed like this for software jobs, and thought it worked well. Just 1 page worth of code, riddled with glaring errors, subtle errors, security issues, code smells, etc. Naturally, spotting more things and more subtle things faster is good.

Re: Reviewing Bad Schematics as EE Interview Tactic

#63
post #37

> Then, you give them a fake schematic of the circuit board, and ask them to troubleshoot the problem. > Here’s the test: the fake board schematic should be absolutely riddled with errors. All sorts of errors - errors that you’ve seen before, errors that you’ve heard about before, errors that have thrown your product development efforts for a loop. These errors should run the gamut of severity I think you need to com…

Just give your opinion as you would to a coworker on your best day. That's what any reasonable interviewer is looking for unless otherwise stated. Similarly, you can tell a lot by how your comments are received.

"Whoever drew this wasn't just high, they smoked all the crack everywhere."

Re: Reviewing Bad Schematics as EE Interview Tactic

#64

I had one of these for an interview a few months ago. A huge schematic and I was told to find out "why it wouldn't work". It took me about 10 minutes to figure out that one FET's diode network was set up so that it'd short out and fail, and I ended up failing the interview for taking so long and labeling every subsection. They told me this was a spot test, and this kind of thing should just jump out immediately if yo…

Sounds like the interviewer tried to use this tactic, and did a lousy job of applying it.

1) "Why it wouldn't work" is vague and nonspecific. "Applying power and hearing a pop/smelling smoke" is a big hint. You have to phrase the question in a way that gives up some information for it to be a decent use of time.

2) Complexity fucking kills these interviews. You shouldn't be handing off a multi-page schematic with complex interconnects. Five or six major components, max. Label your subsections for clarity: things like "microcontroller", "EEPROM", "LED driver", "half bridge driver", "ADC", etc.

Sounds like you did the right thing, and got penalized for it. Fuck 'em. They weren't the right fit for you anyway.

Re: Reviewing Bad Schematics as EE Interview Tactic

#65
I love that idea. I always try to be cognizant of the stress thing too. I cannot count the number of times I've given the candidate a problem based on some basic EE or CS concept, only to have them over-think the heck out of it because the answer seemed "too easy."

While its interesting to see what vector their over-thinking takes, it doesn't help move the interview along.

Doing similar examples with code is also good, as debugging is probably a big chunk of the time people will spend on things. And there are various shades of bug from "in your face" like you have an if statement in C or C++ that uses only one = sign, to "subtle" where a local definition masks a global variable, to just plain ridiculous like structure packing alignment issues based on compiler options.

All good ways to see how much of the 'craft' the candidate knows versus the 'facts'.

Re: Reviewing Bad Schematics as EE Interview Tactic

#66

I love that idea. I always try to be cognizant of the stress thing too. I cannot count the number of times I've given the candidate a problem based on some basic EE or CS concept, only to have them over-think the heck out of it because the answer seemed "too easy." While its interesting to see what vector their over-thinking takes, it doesn't help move the interview along. Doing similar examples with code is also goo…

Thanks Chuck. :)

Re: Reviewing Bad Schematics as EE Interview Tactic

#67
post #12

Earlier quoted context omitted.

I'm an EE. My first job out of university had a pretty good whiteboard interview (I know - we're not supposed to say good things about whiteboard interviews on HN). I thought the process was pretty straightforward. The first exchange went something like this: Interviewer: "Can you draw me the schematic symbol for an LED?" Me: Draws LED schematic symbol. Interviewer: "What would you say the forward voltage is on that…

Do EEs have to do any projects as part of their curriculum. I'm just an SE by training, but have done some electronics purely as a hobby. A power, resistor, LED circut is bassically my hello world for any electronics project I do. I cant imagine getting through any of my hobby projects without calculating an LED resistor at least 1. Although, at this point I always use the same LEDs, so I could get away with just loo…

Yeah, every EE program that I’m aware of has lab courses where you build things on a breadboard, learn to use the oscilloscope and logic analyzer, and probably accidentally let the magic smoke escape from a couple ICs.

However, you’re often working in groups, so it’s not uncommon for one person to really “get it” while the other members of the group nod along but don’t fully understand the choices being made. In addition, TAs in the lab probably don’t have industry experience, so there are basic practical circuit design practices that aren’t taught or enforced.

Labs are a good way to get initial experience, but I think there’s a lot that you inevitably have to learn on the job. There’s a reason you can’t earn a license as a Professional Engineer until you have 4 years of work experience.

Re: Reviewing Bad Schematics as EE Interview Tactic

#68

I had one of these for an interview a few months ago. A huge schematic and I was told to find out "why it wouldn't work". It took me about 10 minutes to figure out that one FET's diode network was set up so that it'd short out and fail, and I ended up failing the interview for taking so long and labeling every subsection. They told me this was a spot test, and this kind of thing should just jump out immediately if yo…

Hard to say for sure, since I don't know you or the company and can't see the test myself. It is a legitimate skill, especially in higher-level engineering positions, to take a huge pile of code or schematics or whatever and get a high-level understanding of what it seems to be doing without getting too bogged down in over-analyzing any particular sub-section too soon. Some things do tend to jump out easily when you have a sufficient level of experience with the overall domain.

Re: Reviewing Bad Schematics as EE Interview Tactic

#69

We've used what we call the "Kobayashi Maru" coding exercise with developers. It was code deliberately filled with various errors, from JavaDoc with @param names not matching argument names, to generic issues, to more subtle issues. One of the last ones involved threading and concurrent access. It also had a test suite to help candidates gauge their progress for programmatic issues, not so helpful for code style issu…

Slightly sad to hear you dropped it — that sounds like fun!

Re: Reviewing Bad Schematics as EE Interview Tactic

#70

I had one of these for an interview a few months ago. A huge schematic and I was told to find out "why it wouldn't work". It took me about 10 minutes to figure out that one FET's diode network was set up so that it'd short out and fail, and I ended up failing the interview for taking so long and labeling every subsection. They told me this was a spot test, and this kind of thing should just jump out immediately if yo…

Sounds like the interviewer tried to use this tactic, and did a lousy job of applying it. 1) "Why it wouldn't work" is vague and nonspecific. "Applying power and hearing a pop/smelling smoke" is a big hint. You have to phrase the question in a way that gives up some information for it to be a decent use of time. 2) Complexity fucking kills these interviews. You shouldn't be handing off a multi-page schematic with com…

Ok, to be fair, they did say "when we turned it on, part of it blew up" when I asked for more details, and it was just a 2-page schematic with 6-7 subsections. I think it was pretty fair, I'm just frustrated that it felt like I couldn't solve it by thinking slowly and methodically.

It was a really cool company and I'd have loved to work there. It's the kind of place where I want to be a good fit.

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