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Reviewing Bad Schematics as EE Interview Tactic

cushychicken.github.io

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Re: Reviewing Bad Schematics as EE Interview Tactic

#51

Post by PascLeRasc »

I had one of these for an interview a few months ago. A huge schematic and I was told to find out "why it wouldn't work". It took me about 10 minutes to figure out that one FET's diode network was set up so that it'd short out and fail, and I ended up failing the interview for taking so long and labeling every subsection. They told me this was a spot test, and this kind of thing should just jump out immediately if you're smart enough. They also said me immediately jumping into the details of each component and its role was a red flag and they didn't think I'd be able to get the big picture of circuit design.

I've been thinking about this since and I don't know how I can fix this. I just don't know any other way to think other than looking at the details. Does their assessment that this is a flaw seem on point?

Re: Reviewing Bad Schematics as EE Interview Tactic

#52

Post by PascLeRasc »

userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

My EE education didn’t cover decoupling caps, and from talking to others from different schools they didn’t learn it either. It's something that only comes out in DIY projects, and unfortunately most schools don't care about projects or fostering independent/continuous learning.

Re: Reviewing Bad Schematics as EE Interview Tactic

#53

Post by ohazi »

rightbyte wrote: post #13
userbinator wrote: post #6

Earlier quoted context omitted.

how should you know that the voltage regulator doesn't have internal caps without seeing the specs? Can you name one voltage regulator that has them? Maybe you've worked with a few, but just off the top of my head, the 78xx, 317, and 1117 don't, and neither do all the other miscellaneous ones that I've seen in consumer electronics.

Traco Power has some. I don't know which one we used on the top of my head but kinda like this with fewer pins: https://www.tracopower.com/products/browse-by-category/find/... It's not my field and I had little clue what was happening at the EE level. Maybe you could argue they are not what is normally meant by saying voltage regulators.

That's a module, not a chip. If it's one of those 1mm x 2mm sot packages, it almost certainly doesn't have embedded switching capacitors.

Re: Reviewing Bad Schematics as EE Interview Tactic

#54

Post by peter_d_sherman »

Excerpt:

"Need some ideas for a crappy schematic? Here are some easy ones I can think up off the cuff:

o Current limiting resistors missing (BJTs, diodes, etc.)

o Shorting a potentiometer node to a rail

o Voltage regulators missing capacitors at input/output

o Missing pull-up/pull-down resistors on digital buses

o Missing decoupling capacitors

o Powering ADC reference voltages from a switching supply

o Transistors placed in wrong/backwards configuration

o No signal conditioning/buffer for analog signals into ADC

o AC coupling high-pass filter sets corner frequency too high into ADC

o Reset sequence of digital component is wrong

o Antenna is missing a matching network/filter

o Clock/data lines swapped backwards in digital bus

o No pull-up/pull-down resistors on IC configuration pins

o No frequency compensation on unstable opamp circuits

o Improper gain settings on opamp circuits"

Fascinating!

Would love to see a book about these errors and others -- with the title:

"Learn EE (better!) -- by studying things that don't work"

The book could be divided into chapters... Each chapter delves into another way that a circuit can fail, along with an explanation of why, and the correct way to engineer that type of circuit/circuit component... The chapters would be ordered from the most common errors to the less common ones... it would be a great teaching tool for people who wanted to become better at EE...

Re: Reviewing Bad Schematics as EE Interview Tactic

#55

Post by cushychicken »

userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

I didn't expect when I wrote this post that the decoupling caps comment would be the one that starts the HN flame thread. XD

Re: Reviewing Bad Schematics as EE Interview Tactic

#56

Post by [deleted] »

imba404 wrote: post #49
madengr wrote: post #22

Here are some of my RF specific interview questions. Spend no more than 1 minute on each. Power Amplifiers Q: Where do GaAs/GaN FETs DC gate currents originate, and why are they positive and negative? Q: How would you temperature compensate the transistor DC bias. Q: What is AM-AM and AM-PM distortion and how would you measure it? Q: Give an example of a “memory effect”. Passive RF/Microwave Circuits Q: How would you…

Dude, I work in RF and it would take me more than a minute to remember some of the answers to these questions.

[deleted]

Re: Reviewing Bad Schematics as EE Interview Tactic

#57

Post by cushychicken »

Treblemaker wrote: post #32

I get that this is intended to be a general exercise in spotting schematic errors. But as someone who brought-up and debugged numerous complex power supply boards for mobile electronics, it seems to me the most important and useful bit of information is missing from this exercise: show me where the smoke came out!

I considered including the actual one page PDF I use for interviews in the post, but I didn't want to chance someone finding it online before they came into an interview with me.

But yes, the central point of the exercise is "show me where the smoke came out!" (It's a very, very dumb mistake. Nearly everyone I've spoken to has reasoned their way to it.)

The rest of it is to let people demonstrate what other errors they can pick out, or serve as fallbacks for the folks who don't find the magic smoke/component death failure.

Re: Reviewing Bad Schematics as EE Interview Tactic

#58

Post by sitkack »

PascLeRasc wrote: post #51

I had one of these for an interview a few months ago. A huge schematic and I was told to find out "why it wouldn't work". It took me about 10 minutes to figure out that one FET's diode network was set up so that it'd short out and fail, and I ended up failing the interview for taking so long and labeling every subsection. They told me this was a spot test, and this kind of thing should just jump out immediately if yo…

I think you lucked out actually. Interviews go both ways.

Re: Reviewing Bad Schematics as EE Interview Tactic

#59

Post by cushychicken »

peter_d_sherman wrote: post #54

Excerpt: "Need some ideas for a crappy schematic? Here are some easy ones I can think up off the cuff: o Current limiting resistors missing (BJTs, diodes, etc.) o Shorting a potentiometer node to a rail o Voltage regulators missing capacitors at input/output o Missing pull-up/pull-down resistors on digital buses o Missing decoupling capacitors o Powering ADC reference voltages from a switching supply o Transistors pl…

I've never heard of a whole book, but I can see how it'd be a great book if someone really took the time to make it.

I guess you could argue that The Art of Electronics kind of fills this niche. Horowitz and Hill call out a bunch of non-functional or error prone circuits with large, friendly "DON'T DO THIS" labels. The second edition had a great section at the end of each chapter entitled "Bad Circuits" that served just this purpose. (The only flaw with the 3rd edition is that they took out "Bad Circuits", in my opinion.)

Re: Reviewing Bad Schematics as EE Interview Tactic

#60

Post by sitkack »

rightbyte wrote: post #15
spatular wrote: post #7

Earlier quoted context omitted.

I've yet to see a voltage regulator IC with built-in caps. DC-DC modules sure, but author argues that this kind of info (module / ic) should be present in schematics. BTW, some linear regulators can't handle ceramic and low-ESR capacitors at output, and may be better with none if that's the choise.

I hate to maybe be proving his point by showing that I'm not into the EE field and thinking of a board mounted DCDC-converter as a voltage regulator (which it is but not what you usually call it in english?) I would still argue that logic IC have alot of internal pull ups. Or that eg. "Reset sequence of digital component is wrong" is a bad whiteboard question.

ICs with multiple power domains have a boot sequence that must be followed or the IC isn't in the proper state. Many interview questions fall into the "assumed assumptions" category. Simply saying, "lets reset to a known good state and modify one variable at time disqualifies many candidates". Because we don't teach science like we should. We should be teaching the scientific method before we teach the three Rs.
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