Earlier quoted context omitted.
And a lot of interviewers report that all juniors fail FizzBuzz.
I just refuse to believe this. It can’t be.
Reviewing Bad Schematics as EE Interview Tactic
41–50 of 111 posts
Re: Reviewing Bad Schematics as EE Interview Tactic
#42I’ve tried (and abandoned) a similar question suite for Security SWEs. Giving people sample code riddled with security flaws and asking them to explain what was wrong. I found it difficult in the security domain since so much of it is context dependent (what’s the interface? Is this code in the kernel? Are you concerned about speculative side channels?). I also found it difficult to calibrate. There’s probably a good…
Re: Reviewing Bad Schematics as EE Interview Tactic
#43> Then, you give them a fake schematic of the circuit board, and ask them to troubleshoot the problem. > Here’s the test: the fake board schematic should be absolutely riddled with errors. All sorts of errors - errors that you’ve seen before, errors that you’ve heard about before, errors that have thrown your product development efforts for a loop. These errors should run the gamut of severity I think you need to com…
Re: Reviewing Bad Schematics as EE Interview Tactic
#44Earlier quoted context omitted.
I hate to maybe be proving his point by showing that I'm not into the EE field and thinking of a board mounted DCDC-converter as a voltage regulator (which it is but not what you usually call it in english?) I would still argue that logic IC have alot of internal pull ups. Or that eg. "Reset sequence of digital component is wrong" is a bad whiteboard question.
I believe that without qualification "linear regulator" could be just anything that regulate voltage. Usually you can easily tell from schematics around it if it's some switching IC, an LDO or a module. And if you have layout or 3d render of the board it'd be almost certain. Otherwise the person may just ask: "where are caps, or is this thing a module or what?"
Definitely not a switcher or module, could be an LDO.
Re: Reviewing Bad Schematics as EE Interview Tactic
#45Earlier quoted context omitted.
And a lot of interviewers report that all juniors fail FizzBuzz.
I just refuse to believe this. It can’t be.
It would be great if they'd stumble over conundrums like "what if there are non-numeric entries in the array." Most often, they just stare and don't even start on the problem.
Re: Reviewing Bad Schematics as EE Interview Tactic
#46Earlier quoted context omitted.
It seems strange that the author has not met a single one that understands that concept since it is quite basic. I am guessing he just is bad at interviewing and asks trick questions till he meet someone who know the interviewing game inside out. Examples he gives: "Current limiting resistors missing (BJTs, diodes, etc.) Shorting a potentiometer node to a rail Voltage regulators missing capacitors at input/output Mis…
how should you know that the voltage regulator doesn't have internal caps without seeing the specs? Can you name one voltage regulator that has them? Maybe you've worked with a few, but just off the top of my head, the 78xx, 317, and 1117 don't, and neither do all the other miscellaneous ones that I've seen in consumer electronics.
How should you know if the lack of input filtering is because of poor design vs the fact that the spec of the power supply changed and you no longer need it?
If it’s not universally true and obvious it’s not a good test.
Modern boards are super complex I’m not an EE but I would more likely flag lacking probe points, probe points which are too far or too close apart or too far from common ground as bad design choices than try to figure out if there are enough caps for the voltage regulator without knowing the full specs of the damn thing.
For all i know that voltage regulator isn’t even being used anymore because the IC or PSU specs have changed mid production but because it was wave soldered with a different soldering method than the other SMTs they already had them on a bunch of boards...
If you can’t reverse engineer the board or the relevant within a few min it shouldn’t be in an interview.
Not an EE but I do a lot of HW RE if anyone puts a modern multi layer doubled sided board on my lap and tells me to point out what’s wrong with it in an interview I would ask them what’s wrong with them.
Re: Reviewing Bad Schematics as EE Interview Tactic
#47My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.
I'm an EE. My first job out of university had a pretty good whiteboard interview (I know - we're not supposed to say good things about whiteboard interviews on HN). I thought the process was pretty straightforward. The first exchange went something like this: Interviewer: "Can you draw me the schematic symbol for an LED?" Me: Draws LED schematic symbol. Interviewer: "What would you say the forward voltage is on that…
Re: Reviewing Bad Schematics as EE Interview Tactic
#48Re: Reviewing Bad Schematics as EE Interview Tactic
#49Here are some of my RF specific interview questions. Spend no more than 1 minute on each. Power Amplifiers Q: Where do GaAs/GaN FETs DC gate currents originate, and why are they positive and negative? Q: How would you temperature compensate the transistor DC bias. Q: What is AM-AM and AM-PM distortion and how would you measure it? Q: Give an example of a “memory effect”. Passive RF/Microwave Circuits Q: How would you…
Re: Reviewing Bad Schematics as EE Interview Tactic
#50>>> Then, you give them a fake schematic of the circuit board, and ask them to troubleshoot the problem. Is the board built to the schematic? That's my first question when a board loses its magic smoke.