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Coming Soon: AWS Graviton2 Processor for AWS

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Re: Coming Soon: AWS Graviton2 Processor for AWS

#101

Post by solidasparagus »

goosehonk wrote: post #67
dman wrote: post #10

If Intel makes it out of the current soup with its dominance intact it will make for an interesting case study. Think they are facing the perfect storm on multiple fronts. a. The 10nm process fiasco b. Missing the chiplet concept c. ISA fragmentation - AVX512 which was supposed to be the next big thing was server CPU side only till recently and downclocks the entire chip when used making it extremely hard to reason a…

This comment seems kinda slanted. AVX-512 debuted on Xeon because datacenter operators asked for it. It does not “downclock a whole chip”, it gates the core where it is active and there’s not even that penalty on the current generation parts. “10nm” is marketing fluff which has little or nothing to do with actual semiconductor construction. “Chiplet” is also marketing-speak for “wow this memory topology is hard to pr…

Uhh source on AVX512 not downclocking on modern CPUs? We benchmarked ML workloads on the newest chips the cloud had to offer and the slowdown was a significant problem because, as the parent comment said, it is very hard to reason about whether the benefits of vectorized ops will outweigh the the reduced clock speed. Sometimes it does and sometimes it does not - which is a major problem when you have to specify instruction set when you build the ML library from source.

Maybe you know something I don’t but that FPGA statement makes zero sense to me. The ASIC development cycle is measured in years - that’s why FPGA’s are valuable (and I thought they were relatively heavily used).

Re: Coming Soon: AWS Graviton2 Processor for AWS

#102

Post by amluto »

dman wrote: post #10

If Intel makes it out of the current soup with its dominance intact it will make for an interesting case study. Think they are facing the perfect storm on multiple fronts. a. The 10nm process fiasco b. Missing the chiplet concept c. ISA fragmentation - AVX512 which was supposed to be the next big thing was server CPU side only till recently and downclocks the entire chip when used making it extremely hard to reason a…

Also, Intel is bizarrely behind on PCIe. Historically, a data center machine with big expensive GPUs or other accelerators also had a couple of expensive Xeons in it. Right now, AMD has a much better offering even ignoring cost. I’m sure someone outside x86 (Amazon? ARM itself? POWER?) will jump in, too.

Re: Coming Soon: AWS Graviton2 Processor for AWS

#103

Post by solidasparagus »

StillBored wrote: post #99
kevin_thibedeau wrote: post #90

Earlier quoted context omitted.

Chiplets are more significant than you credit them for. They allow higher yields and make the production economics much more favorable for AMD, whereas Intel is throwing out a lot more silicon.

Yield might be part of it, but I'm sure intel can ship partially functional chips with a core here/there disabled. Another of the big advantages for AMD is that their products aren't reticle limited. The basic design lets them have a single design they bolt into dozens of configurations that scale larger than what intel can fit on a single die. Hence 64 "big" cores in a single socket. There are likely other advantage…

Chips with problematic cores are sold as lower end chips. For the same production cost, you are getting less revenue - failure rate plays a big role in profit margins.

Re: Coming Soon: AWS Graviton2 Processor for AWS

#104

Post by StillBored »

goosehonk wrote: post #69
jonstewart wrote: post #47

Earlier quoted context omitted.

Well, and for 25-30 years, everyone’s been crowing about how they were doomed to fail because of x86 as a CISC design. Intel killed off most RISC competitors as Moore’s Law held in the 90 and they could just add more transistors to turn x86 into a facade. But that increase in transistors and doing whatever possible to keep x86 performant meant they were doomed to lose the power/performance war that came with mobile p…

ARM has never enjoyed a Op/J advantage over x86. They have low-power designs, yes, but they don’t do more work for a given amount of energy. x86 won fair and square. The risc people failed to foresee that instruction density would be extremely important to performance. Intel didn’t beat them with physics. CISC is just fundamentally better.

ARM has never enjoyed a Op/J advantage over x86.

I'm not sure that exactly accurate, its more accurate to say, that there was a lack of market crossover that allowed similar power or perf envelopes.

That is because ARM did/does make much more efficient CPU's, they just aren't anywhere close to the perf of common x86 cores. AKA a low clocked in order ARM with small caches, etc is more efficient per op but it can't touch even a medium size x86. Intel sort of was in that market for a bit and their cores were efficient too, but the main selling point for an architecture is the software around it, and a 50 mhz in-order x86 can't exactly run modern windows in a reasonable way.

Now that ARM & friends are building higher perf parts, the power efficiency keeps getting worse. When someone makes a 5Ghz ARM core it will likely consume more than a couple mW.

The perf/power ratios have more to do with culture and market than ISA.

Re: Coming Soon: AWS Graviton2 Processor for AWS

#105

Post by [deleted] »

solidasparagus wrote: post #101
goosehonk wrote: post #67

Earlier quoted context omitted.

This comment seems kinda slanted. AVX-512 debuted on Xeon because datacenter operators asked for it. It does not “downclock a whole chip”, it gates the core where it is active and there’s not even that penalty on the current generation parts. “10nm” is marketing fluff which has little or nothing to do with actual semiconductor construction. “Chiplet” is also marketing-speak for “wow this memory topology is hard to pr…

Uhh source on AVX512 not downclocking on modern CPUs? We benchmarked ML workloads on the newest chips the cloud had to offer and the slowdown was a significant problem because, as the parent comment said, it is very hard to reason about whether the benefits of vectorized ops will outweigh the the reduced clock speed. Sometimes it does and sometimes it does not - which is a major problem when you have to specify instr…

[deleted]

Re: Coming Soon: AWS Graviton2 Processor for AWS

#106

Post by StillBored »

kbenson wrote: post #29
rb808 wrote: post #19

Its interesting but I wouldn't say Graviton2 is likely to succeed. Every ARM based PC I've seen has been disappointingly slow, which I dont really understand because phones usually are amazingly quick. DEC Alpha, Sun Sparc, MIPS, PowerPC couldn't keep up with Intel in the recent past either. Intel CPUs aren't cheap, but they're a fraction of the cost of a server. All adds up to interesting innovation but not necessar…

> Intel CPUs aren't cheap, but they're a fraction of the cost of a server. Depending what what performance level you're looking at, they're a very large fraction of the server cost. Get a dual or quad socket board and buy the higher end CPUs and you might be looking at well over half the cost.

I think the point is that, if your buying a quad socket, the 2TB of ECC ram you stick in it will dwarf the core prices, or similarly its not hard to drop $50k on U.2 NVMe, etc.

Its possible to shift this argument different ways depending on the part of the market your looking at.

Re: Coming Soon: AWS Graviton2 Processor for AWS

#107

Post by amluto »

goosehonk wrote: post #69
jonstewart wrote: post #47

Earlier quoted context omitted.

Well, and for 25-30 years, everyone’s been crowing about how they were doomed to fail because of x86 as a CISC design. Intel killed off most RISC competitors as Moore’s Law held in the 90 and they could just add more transistors to turn x86 into a facade. But that increase in transistors and doing whatever possible to keep x86 performant meant they were doomed to lose the power/performance war that came with mobile p…

ARM has never enjoyed a Op/J advantage over x86. They have low-power designs, yes, but they don’t do more work for a given amount of energy. x86 won fair and square. The risc people failed to foresee that instruction density would be extremely important to performance. Intel didn’t beat them with physics. CISC is just fundamentally better.

I suspect that, at least for lower-power or lower-area designs, a compact ISA with a friendlier encoding than x86 would be a win. A significant problem with x86 is that a high-performance core needs to decode multiple instructions per cycle, but x86 has a nasty problem that the length of an instruction can’t be determined until it’s fully decoded. I think that modern front-ends try all possible offsets at once and throw out the wrong guesses. This costs area and power.

A design where all instructions have one of just a few sizes and where the first byte unambiguously encodes the length would be nicer.

RISV-V is decent in this respect.

FWIW, x86’s legacy is a security problem, too. The ISA is so overcomplicated that nasty interactions cause all manner of security bugs. As a recent example, the sequence mov (ptr), %ss; syscall with a data breakpoint at ptr could be used to root most kernels. With virtualization, this type of thing is much worse. A hypervisor needs to handle all the nasty corner cases in a guest user program without crashing itself or the guest kernel, and it needs to handle all the nasty corner cases in guest kernels without dying. There are various ways that native kernels can literally put the microcode in an infinite loop, and hypervisors need complex mitigations because an infinite-looping microcode bug triggered by a guest can’t be preempted by the host, and it will take down the system.

So yes, x86 is not fantastic.

Re: Coming Soon: AWS Graviton2 Processor for AWS

#108

Post by 3fe9a03ccd14ca5 »

privateSFacct wrote: post #63
brianwawok wrote: post #9

Earlier quoted context omitted.

Winning a benchmark isn’t winning. Winning sales is winning. Last I heard most sales still go to intel. But exciting times if this flips, competition is good for all

It's very hard to buy prebuilt AMD products into the enterprise still in my experience

It’s generally hard to buy AMD CPUs period.

Re: Coming Soon: AWS Graviton2 Processor for AWS

#109

Post by StillBored »

solidasparagus wrote: post #103
StillBored wrote: post #99

Earlier quoted context omitted.

Yield might be part of it, but I'm sure intel can ship partially functional chips with a core here/there disabled. Another of the big advantages for AMD is that their products aren't reticle limited. The basic design lets them have a single design they bolt into dozens of configurations that scale larger than what intel can fit on a single die. Hence 64 "big" cores in a single socket. There are likely other advantage…

Chips with problematic cores are sold as lower end chips. For the same production cost, you are getting less revenue - failure rate plays a big role in profit margins.

Vs throwing the whole die away because you don't sell enough systems that small?

Its hard to tell, but intel still has a strong markup on 24 core parts being sold from 28 core dies. Intel has often be "caught" down selling parts to protect their higher margin parts. (AKA they are selling parts with things disabled that work)

Re: Coming Soon: AWS Graviton2 Processor for AWS

#110

Post by amluto »

atq2119 wrote: post #52
jonstewart wrote: post #47

Earlier quoted context omitted.

Well, and for 25-30 years, everyone’s been crowing about how they were doomed to fail because of x86 as a CISC design. Intel killed off most RISC competitors as Moore’s Law held in the 90 and they could just add more transistors to turn x86 into a facade. But that increase in transistors and doing whatever possible to keep x86 performant meant they were doomed to lose the power/performance war that came with mobile p…

Little endian has nothing to do with CISC vs RISC or x86 though. Everybody is little endian today. x86 helped with that historically, certainly, but fundamentally endianness just doesn't matter most of the time, and when it does, little endian makes more sense from first principles.

I think big endian is better: with little endian, treating a pointer to one size integer as a pointer to a different size integer has a decent chance of working, which allows bugs and sloppiness to fester. With big endian, screwing up your pointer type is very unlikely to work, which is IMO a good thing.
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