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Deep Learning and Its Implications for Computer Architecture and Chip Design

arxiv.org

21–26 of 26 posts

Re: Deep Learning and Its Implications for Computer Architecture and Chip Design

#21
post #18

Potentially noob question, with Moore's law slowing down, are there enough specializations/hardware modifications available like those mentioned in the paper such that progress in ML will continue to progress rapidly? or will these advancements simply forestall an inevitable asymptote.

It's little more than an educated guess on my part, but I figure there's about two orders of magnitude in improvements in processing speed exploitable with current processes, if a big-budget chip were designed specifically for ML training. GPUs are architecturally not very optimal for the task. You want something like a chip with a huge mesh of small independent cores with their own local storage, quite possibly with…

This doesn't seem to match my experience with ML and GPUs/ASICs.

TPU is the main ML ASIC in use. A major goal of the original TPU design seems to be reducing the number of memory accesses. The other top-end ML device is NVIDIA's GPUs with Tensor Cores. Both of those chips are designed around fast matrix multiplication, which right now seems to be the most important operation in deep learning - see how RNNs have started to fall out of favor to CNN-based networks with attention heads.

The TPU is not faster than NVIDIA's GPUs, but it is cheaper. Right now the future seems to be cheaper ML devices designed to be horizontally scalable.

From the CPU perspective, it appears that the major ML effort is related to vectorizing instructions via advanced instruction sets.

Everyone who creates silicon is focused very heavily on using smaller and smaller numeric types - float16 is standard and there is work being done for even smaller int based work.

I haven't seen any analog-based ML devices in use. Can you share an example? Is there even a way to approximate the results of a matmul using analog devices?

It's impossible to guess how much more speed we can get with current approaches, but everything from silicon to networking stack to libraries to network architectures are in their infancy so I would expect dramatic improvements in performance on a regular basis (but not as regular as other areas of software because silicon development is slow)

Re: Deep Learning and Its Implications for Computer Architecture and Chip Design

#22
post #4

Does anyone happen to have a link to a paper or book describing the state of the art in placement and routing algorithms? I'd like to read up on that topic.

This is a really interesting paper on using RL for device placement - https://ai.google/research/pubs/pub46646.

Re: Deep Learning and Its Implications for Computer Architecture and Chip Design

#23
post #7

Earlier quoted context omitted.

Read it. Worth a read, especially for those not closely following the machine learning world. The last section, focussing on having a single large sparsely activated model which can accomplish thousands of different tasks by using a selection of internal 'experts' interests me the most. I suspect this type of model isn't used much today simply because each company using ML only typically has a few problems to solve.…

Sparsely activated multitask model is a kind of Jeff Dean's hobby horse. It was published in 2017: https://arxiv.org/abs/1701.06538 . My assessment is that it is an intriguing but ultimately failed experiment, like Geoffrey Hinton's capsule network.

Risky to say, considering deep learning by Hinton was also once called a failed experiment ...

Re: Deep Learning and Its Implications for Computer Architecture and Chip Design

#24
> Figure 2 shows this dramatic slowdown, where we have gone from doubling general-purpose CPU performance every 1.5 years (1985 through 2003) or 2 years (2003 to 2010) to now being in an era where general purpose CPU performance is expected to double only every 20 years [Hennessy and Patterson 2017].

This isn't true. CPU performance has stagnated very recently due to Intel's struggles with 10nm, but we look to be leaving that behind us. Even if we weren't, it's still not relevant for ML, since within the last decade GPUs have improved a factor of ~10—thus the terrifying Figure 2 is proven false.

Re: Deep Learning and Its Implications for Computer Architecture and Chip Design

#25
post #18

Earlier quoted context omitted.

It's little more than an educated guess on my part, but I figure there's about two orders of magnitude in improvements in processing speed exploitable with current processes, if a big-budget chip were designed specifically for ML training. GPUs are architecturally not very optimal for the task. You want something like a chip with a huge mesh of small independent cores with their own local storage, quite possibly with…

This doesn't seem to match my experience with ML and GPUs/ASICs. TPU is the main ML ASIC in use. A major goal of the original TPU design seems to be reducing the number of memory accesses. The other top-end ML device is NVIDIA's GPUs with Tensor Cores. Both of those chips are designed around fast matrix multiplication, which right now seems to be the most important operation in deep learning - see how RNNs have start…

TPU v3 is rated 420 teraflops, while V100 GPU is rated 125 teraflops.

Re: Deep Learning and Its Implications for Computer Architecture and Chip Design

#26
post #25

Earlier quoted context omitted.

This doesn't seem to match my experience with ML and GPUs/ASICs. TPU is the main ML ASIC in use. A major goal of the original TPU design seems to be reducing the number of memory accesses. The other top-end ML device is NVIDIA's GPUs with Tensor Cores. Both of those chips are designed around fast matrix multiplication, which right now seems to be the most important operation in deep learning - see how RNNs have start…

TPU v3 is rated 420 teraflops, while V100 GPU is rated 125 teraflops.

What does TPU v3 mean there? tpu v3.8? In which case you are comparing 8 cores/4 chips to a single GPU which hardly seems fair. It's hard to compare across ASICs. In practice the the largest readily available amount of compute seem to be 8 V100s vs one 'Cloud TPU' (tpu v3.32). Those two have relatively similar performance in practice (FLOPs seem to be a very poor way to compare across ASICs), although TPU is typically several times less expensive.
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