SiFive Announces First RISC-V OoO CPU Core • Hacker News Board

Re: SiFive Announces First RISC-V OoO CPU Core

#31

Post by monocasa » Wed, Oct 30, 2019, 6:25 PM UTC

cesarb wrote: post #15

audunw wrote: post #11

Earlier quoted context omitted.

The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs. If I remember correctly, that's one of the reasons everyone jumped ship from OpenRISC to RISC-V (the big mistake in OpenRISC being branch delay slots I believe) It might also help starting from scratch. I'm also not convinced it's entirely an apples-to-apples comparison. ARM might support more complex instr…

> The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs. ARM's 64-bit architecture (AArch64) was also made with similar hindsight, so that's probably not the whole reason.

Most AArch64 cores still have to support AArch32 modes, and so aren't allowed to take advantage of those optimizations.

Re: SiFive Announces First RISC-V OoO CPU Core

#32

Post by brucehoult » Wed, Oct 30, 2019, 6:25 PM UTC

baybal2 wrote: post #8

> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…

The A72 supports at least three completely different instruction sets (A64, A32, T32), which has a cost. You could make a much sleeker A64-only CPU core as Apple, Cavium, and Fujitsu do, though it's still not going to be as sleek as RISC-V.

Re: SiFive Announces First RISC-V OoO CPU Core

#33

Post by zozbot234 » Wed, Oct 30, 2019, 6:25 PM UTC

AWildC182 wrote: post #22

fulafel wrote: post #2

"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.

God I hate that term. It's not your secret sauce intellectual property, it's a fucking library. Possibly the biggest reason FPGA/ASIC tech has lagged so hard behind CPU/GPGPU in terms of consumer use is because they have managed to use their hardware to completely stifle all open source software (they even go to some lengths to distance themselves from the term "software"). FPGA libraries are almost always encrypted…

Interacting with a PCIe bus does not seem "mundane" to me. Analog electronics is hard, and, just as importantly, process-specific (and the details of any one process are generally kept strictly confidential to the fab, with tightly-binding NDAs). Now, when it comes to pure digital logic I agree, but that's also where open hardware (with meaningful contributions by SiFive themselves) has been most successful.

Re: SiFive Announces First RISC-V OoO CPU Core

#34

Post by monocasa » Wed, Oct 30, 2019, 6:26 PM UTC

kick wrote: post #13

baybal2 wrote: post #8

> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…

SiFive was founded by most of the initial RISC-V designers, and is easily one of the companies with the most raw talent in the field right now.

Yeah, Apple('s acquisitions) are probably the closest in terms of raw talent, and their cores aren't being compared here for a lot of reasons.

Re: SiFive Announces First RISC-V OoO CPU Core

#35

Post by monocasa » Wed, Oct 30, 2019, 6:27 PM UTC

Have we gotten confirmation yet on whether this is a BOOM core or not? It certainly feels like it is

Re: SiFive Announces First RISC-V OoO CPU Core

#36

Post by snvzz » Wed, Oct 30, 2019, 6:36 PM UTC

AWildC182 wrote: post #22

fulafel wrote: post #2

"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.

God I hate that term. It's not your secret sauce intellectual property, it's a fucking library. Possibly the biggest reason FPGA/ASIC tech has lagged so hard behind CPU/GPGPU in terms of consumer use is because they have managed to use their hardware to completely stifle all open source software (they even go to some lengths to distance themselves from the term "software"). FPGA libraries are almost always encrypted…

Hell, I'm glad Symbiflow[0] exists. Once the toolchain is a little more mature, a library of modules with OSHW licenses is bound to pop up, perhaps even integrated into some sort of IDE.

[0] https://symbiflow.github.io/

Re: SiFive Announces First RISC-V OoO CPU Core

#37

Post by snvzz » Wed, Oct 30, 2019, 6:37 PM UTC

mattnewport wrote: post #25

A Raspberry Pi type SBC based on this would be neat, is that something we can expect to see any time soon in light of this announcement or is that not an application this is really aimed at?

This is most likely to come from lowrisc[0] instead.

[0] https://www.lowrisc.org/

Re: SiFive Announces First RISC-V OoO CPU Core

#38

Post by brucehoult » Wed, Oct 30, 2019, 6:39 PM UTC

mattnewport wrote: post #25

A Raspberry Pi type SBC based on this would be neat, is that something we can expect to see any time soon in light of this announcement or is that not an application this is really aimed at?

That would be neat, and would come out somewhere similar to a Pi 4 (which are pretty awesome).

Note that the Pi 4 has ARM processor cores, but ARM doesn't make either the processor chip or the board. Broadcom design and make the BCM2711 SoC, and the Raspberry Pi Foundation designed and manufactures the board.

No doubt SiFive would be very happy to work with someone who wanted to make retail SoCs and/or SBCs using the U84, but as with ARM it's not really their business model to do that themselves.

SiFive has made several low-volume chips and boards for potential core IP customers to use for evaluation and development e.g. the $999 HiFive Unleashed. ARM similarly offers a $10000 dev board for the A72.

Re: SiFive Announces First RISC-V OoO CPU Core

#39

Post by childintime » Wed, Oct 30, 2019, 6:44 PM UTC

yhvh wrote: post #23

Is there a risc-v chip on the market which includes Bluetooth?

Espressif is planning a RISCV based ESP32 upgrade, it'll probably will have Bluetooth. No schedule yet.

Re: SiFive Announces First RISC-V OoO CPU Core

#40

Post by jeanmichelx » Wed, Oct 30, 2019, 6:45 PM UTC

baybal2 wrote: post #8

> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…

I doubt their numbers are correct. They've fudged them in the past, giving area numbers for the smallest configuration, but performance number for a ridiculously large chip.