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Xilinx Vitis and Vitis AI Software Development Platforms

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Re: Xilinx Vitis and Vitis AI Software Development Platforms

#11

Post by [deleted] »

jhallenworld wrote: post #9
kop316 wrote: post #6

"The adoption of FPGA technology in the market has always been limited by the severe learning curve required to take advantage of it." I vehemently disagree with this. FGPAs and their toolchains are notoriously expensive and proprietary. I have no doubt that if tool chains were opened up and an average person could program for it, you would see much more.rapid adoption because then an average person could start the l…

I also disagree. The main problem is much simpler: they cost too much for fundamental reasons. The die-size for an FPGA that would have equivalent power of an Intel CPU or Nvidia GPU would be huge and expensive.

[deleted]

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#12

Post by jhallenworld »

gsmecher wrote: post #7
spamizbad wrote: post #3

Earlier quoted context omitted.

I'm curious: why is FPGA tooling so poor? I used a Spartan-3 over a decade ago for a simple project, and as cursory look it doesn't seem like things have changed much despite the devices becoming significantly more diverse and complicated.

It's not quite fair to say the tooling is flat-out awful. Vivado is much better than ISE. The place/route algorithms matured (analytical placement rather than simulated annealing), and the software it's wrapped in grew up (it's now tcl-driven and much more script- and revision-control-friendly.) Vivado was a heroic effort and Xilinx deserves credit for taking software seriously, and getting so much of it right. If yo…

I'm using Vivado right now. Things I hate about it:

- It's sluggish. The underlying algorithms may be fast (they handle huge designs), but even with an empty design it's sluggish. I'm not sure if this is from the Java or the TCL. On the other handle Altera/Intel Quartus is faster.. (it also uses Java and TCL..)

- I hate TCL. This whole concept of an integrated extension language in a massive tool is terrible. It's the standard way in the EDA world, but it's not good at all. I prefer simpler tools tied together with Makefiles..

- I hate the schematic-like block designs. I just want a single Verilog file that represents the design, no XML. The block designs are difficult to integrate with git.

- I hate projects. They are difficult to integrate with git: you have to export project tcl, then regenerate the project from this checked in file. It's aweful and breaks when the design gets complicated.

- I'm using Zynq Ultrascale+ and I hate eclipse. The EDK is eclipse-based. I just want a command line tool to generate a project from the hardware description so that I never have to open the Eclipse. True, once your hardware is stabilized, you can avoid it (it does generate a Makefile). I've not tried Altera's SoCs, so not sure if better.

That being said, Xilinx did a good job with the BSP software and the Linux support. At least it's better than what we see on some embedded processors (Nvidia, ugh..)

Also I recently ported a design from Zynq (32-bit) to Zynq Ultrascale+ (64-bit). Not bad at all.

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#13

Post by enos_feedler »

rowanG077 wrote: post #8
kop316 wrote: post #6

"The adoption of FPGA technology in the market has always been limited by the severe learning curve required to take advantage of it." I vehemently disagree with this. FGPAs and their toolchains are notoriously expensive and proprietary. I have no doubt that if tool chains were opened up and an average person could program for it, you would see much more.rapid adoption because then an average person could start the l…

This. It's not so hard, any competent software engineer could learn HDLs in one or two weeks. The fucking toolchain though? Months...

It's a chicken and egg problem too. Toolchain friction and depth of knowledge required is one part. Ubiquity of FPGA silicon lying around in the average programmer's (and end-user's) machine is not there.

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#14

Post by gsmecher »

jhallenworld wrote: post #12
gsmecher wrote: post #7

Earlier quoted context omitted.

It's not quite fair to say the tooling is flat-out awful. Vivado is much better than ISE. The place/route algorithms matured (analytical placement rather than simulated annealing), and the software it's wrapped in grew up (it's now tcl-driven and much more script- and revision-control-friendly.) Vivado was a heroic effort and Xilinx deserves credit for taking software seriously, and getting so much of it right. If yo…

I'm using Vivado right now. Things I hate about it: - It's sluggish. The underlying algorithms may be fast (they handle huge designs), but even with an empty design it's sluggish. I'm not sure if this is from the Java or the TCL. On the other handle Altera/Intel Quartus is faster.. (it also uses Java and TCL..) - I hate TCL. This whole concept of an integrated extension language in a massive tool is terrible. It's th…

These are all fair criticisms. Block designs, XML files for project and IP management, and auto-generated .tcl are all bad things. Eclipse sucks.

I understand why vendors ship tools with all of these things. I think (hope?) they're slowly un-bundling more and more of the toolflow so you can avoid them if you want.

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#15

Post by AWildC182 »

8note wrote: post #5
rowanG077 wrote: post #4

Earlier quoted context omitted.

Mostly because it's (almost) all proprietary. None of the companies are investing in a truly usable solution. It speaks volumes that a handful of developers working for free where able to create a vastly better experience with yosys and friends.

I've always imagined they have a good quality version for military applications, and the bad stuff for everyone else

Most of the development is for the military. It gets farmed to contractors who use all the same stuff you have access to, just typically several years out of date.

The ability to fully enumerate and simulate every part of the design gives them a huge hardon even though stuff frequently passes simulation and fails on the silicon. It's very common to see FPGAs in nuclear, military RF, and aerospace applications.

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#16

Post by btashton »

jhallenworld wrote: post #12
gsmecher wrote: post #7

Earlier quoted context omitted.

It's not quite fair to say the tooling is flat-out awful. Vivado is much better than ISE. The place/route algorithms matured (analytical placement rather than simulated annealing), and the software it's wrapped in grew up (it's now tcl-driven and much more script- and revision-control-friendly.) Vivado was a heroic effort and Xilinx deserves credit for taking software seriously, and getting so much of it right. If yo…

I'm using Vivado right now. Things I hate about it: - It's sluggish. The underlying algorithms may be fast (they handle huge designs), but even with an empty design it's sluggish. I'm not sure if this is from the Java or the TCL. On the other handle Altera/Intel Quartus is faster.. (it also uses Java and TCL..) - I hate TCL. This whole concept of an integrated extension language in a massive tool is terrible. It's th…

You can generate the sdk including the makefiles from the command line. I don't think I have opened Eclipse on my latest project.

They also do have some articles on preparing the projects for git which work OK, but yeah there is a lot more to be done.

I'm not sure how you would replace the tcl scripts with makefiles. Most of them contain functions to wire together not build targets.

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#17

Post by Traster »

jhallenworld wrote: post #9
kop316 wrote: post #6

"The adoption of FPGA technology in the market has always been limited by the severe learning curve required to take advantage of it." I vehemently disagree with this. FGPAs and their toolchains are notoriously expensive and proprietary. I have no doubt that if tool chains were opened up and an average person could program for it, you would see much more.rapid adoption because then an average person could start the l…

I also disagree. The main problem is much simpler: they cost too much for fundamental reasons. The die-size for an FPGA that would have equivalent power of an Intel CPU or Nvidia GPU would be huge and expensive.

That's simply not right. The FPGA in your NIC is much more powerful for packet processing than any CPU or GPU. Yes, the CPU is better at being a CPU- but that's just a matter of using the right tool for the job.

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#18

Post by [deleted] »

jhallenworld wrote: post #9
kop316 wrote: post #6

"The adoption of FPGA technology in the market has always been limited by the severe learning curve required to take advantage of it." I vehemently disagree with this. FGPAs and their toolchains are notoriously expensive and proprietary. I have no doubt that if tool chains were opened up and an average person could program for it, you would see much more.rapid adoption because then an average person could start the l…

I also disagree. The main problem is much simpler: they cost too much for fundamental reasons. The die-size for an FPGA that would have equivalent power of an Intel CPU or Nvidia GPU would be huge and expensive.

[deleted]

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#19

Post by PAGAN_WIZARD »

rowanG077 wrote: post #8
kop316 wrote: post #6

"The adoption of FPGA technology in the market has always been limited by the severe learning curve required to take advantage of it." I vehemently disagree with this. FGPAs and their toolchains are notoriously expensive and proprietary. I have no doubt that if tool chains were opened up and an average person could program for it, you would see much more.rapid adoption because then an average person could start the l…

This. It's not so hard, any competent software engineer could learn HDLs in one or two weeks. The fucking toolchain though? Months...

Ive seen plenty of HDL written by people who are software engineers, it's not good. It seems to me most software engineers struggle with visualizing their behavioral code as a schematic and tend to write code that is not very synthesis friendly and overly convoluted. Not to mention most issues with hardware engineering cant be solved by a google search of how to do X in Verilog/VHDL, problems tend to be device specific which means you NEED to understand your tool chain and can't abstract away the code from from the implementation like you can with most high level software to the ASM/binary.

Re: Xilinx Vitis and Vitis AI Software Development Platforms

#20

Post by kbob »

enos_feedler wrote: post #13
rowanG077 wrote: post #8

Earlier quoted context omitted.

This. It's not so hard, any competent software engineer could learn HDLs in one or two weeks. The fucking toolchain though? Months...

It's a chicken and egg problem too. Toolchain friction and depth of knowledge required is one part. Ubiquity of FPGA silicon lying around in the average programmer's (and end-user's) machine is not there.

Silicon availability has recently been solved. There are FPGA dev boards available for under $50. They're low-powered but great to learn on. One, the FOMU, actually fits inside a USB type-A port.
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