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A computer built from NOR gates: inside the Apollo Guidance Computer

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Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#11

Post by saagarjha »

not2b wrote: post #4

Back in the 1990s, UC Berkeley's computer hardware quals exam used to require the test taker to design a microcoded RISC processor out of NAND gates, from the bottom up. It was kind of like Little Alchemy, once you created every kind of primitive gate you needed, you could assemble them to make larger and larger things. This included building latches, registers, static RAM, bottom to top. NOR is just NAND with 0's an…

One of the classes at my university had a tradition of a guest lecturer coming in and give a two hour talk on “building a computer with magnets” at the beginning of the quarter to incoming freshmen. He’d go through pretty much the same things you mentioned, combining smaller components as he went into more complex ones, culminating in a computer that could do a full fetch-decode-execute cycle (whimsically, powered by the turning of a water wheel).

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#12

Post by ncmncm »

dbcurtis wrote: post #8

Back when I was a CPU logic designer, I worked on two machines that used ECL logic, where the basic building-block gate was a 4-input OR/NOR (the gate produced both phases at output). I recall that on one of these machines, each logic card was supplied with well over 100A on the -4.5 supply, we had a space budget of 98 cards. But the tough limit to hit was cooling. For the entire CPU we had only a single 20 BTU-ton w…

Control Data?

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#13

Post by ip26 »

not2b wrote: post #4

Back in the 1990s, UC Berkeley's computer hardware quals exam used to require the test taker to design a microcoded RISC processor out of NAND gates, from the bottom up. It was kind of like Little Alchemy, once you created every kind of primitive gate you needed, you could assemble them to make larger and larger things. This included building latches, registers, static RAM, bottom to top. NOR is just NAND with 0's an…

How much time did you have for this exam? Building a complete processor starting from gates is not exactly a thirty minute exercise, even with a minimal instruction set & narrow datapath.

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#14

Post by frostburg »

ip26 wrote: post #13
not2b wrote: post #4

Back in the 1990s, UC Berkeley's computer hardware quals exam used to require the test taker to design a microcoded RISC processor out of NAND gates, from the bottom up. It was kind of like Little Alchemy, once you created every kind of primitive gate you needed, you could assemble them to make larger and larger things. This included building latches, registers, static RAM, bottom to top. NOR is just NAND with 0's an…

How much time did you have for this exam? Building a complete processor starting from gates is not exactly a thirty minute exercise, even with a minimal instruction set & narrow datapath.

I recall having to do something similar for my "computer architecture" exam (in Italy) in very limited time (it was on paper during an oral examination), but I could get away with a very simple not-even-pipelining design.

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#15

Post by cesarb »

ncmncm wrote: post #7

I was impressed to learn that when Margaret Hamilton programmed this machine, she wrote an interpreter, and coded the mission logic in the interpreted language. So, in a sense, it really was microcoded; but the microcode was what looks like the real instruction set, and the instructions actually used lived in ROM. The Xerox Alto, which was used for the original Smalltalk in 1972, also worked much this way: It had 16…

The author of this article has a whole set of articles on the Xerox Alto (http://www.righto.com/search/label/alto). This one focuses on the microcode: http://www.righto.com/2016/09/xerox-alto-restoration-day-5-s...

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#16

Post by geomark »

dbcurtis wrote: post #8

Back when I was a CPU logic designer, I worked on two machines that used ECL logic, where the basic building-block gate was a 4-input OR/NOR (the gate produced both phases at output). I recall that on one of these machines, each logic card was supplied with well over 100A on the -4.5 supply, we had a space budget of 98 cards. But the tough limit to hit was cooling. For the entire CPU we had only a single 20 BTU-ton w…

I was one generation behind you. We had actual flip/flops and even small ROMs, made from something called CTL (complementary transistor logic) which was similar to ECL in its voltage and power requirements. But did not require water cooling, just banks of large squirrel cage fans.

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#18

Post by anon91831837 »

NOR gate logic, like NAND and NOT/AND/OR gate logic, are functionally-complete.

Combinational logic examples:

- NOT gate -> N-input (N >= 1) NOR with all inputs tied together to the input

- N-input OR gate -> N-input NOR gate with a NOT gate at the output

- N-input AND gate -> N-input NOR gate with a NOT gate in front of each input

- Bonus - sequential logic: S-R latch -> 2x 2-input NOR gates with one each of their inputs tied to the other gate's output

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#19

Post by bctnry »

anon91831837 wrote: post #18

NOR gate logic, like NAND and NOT/AND/OR gate logic, are functionally-complete. Combinational logic examples: - NOT gate -> N-input (N >= 1) NOR with all inputs tied together to the input - N-input OR gate -> N-input NOR gate with a NOT gate at the output - N-input AND gate -> N-input NOR gate with a NOT gate in front of each input - Bonus - sequential logic: S-R latch -> 2x 2-input NOR gates with one each of their i…

should be N >= 2 because you can't really have 1-input NOR gate...?

Re: A computer built from NOR gates: inside the Apollo Guidance Computer

#20

Post by fspeech »

not2b wrote: post #4

Back in the 1990s, UC Berkeley's computer hardware quals exam used to require the test taker to design a microcoded RISC processor out of NAND gates, from the bottom up. It was kind of like Little Alchemy, once you created every kind of primitive gate you needed, you could assemble them to make larger and larger things. This included building latches, registers, static RAM, bottom to top. NOR is just NAND with 0's an…

NAND or NOR preference is due to the underlying transistor technology. NPN transistors (with electron majority carriers) tend to be stronger than PNP types (with hole majority carriers) at comparable sizes. In the beginning we had mostly bipolar processes, where we used NPN transistors in parallel to pull down the output and pull-ups were simply resistors. NOR gate was the natural configuration efficiency/cost wise. Later CMOS processes came along and we no longer use resistors for pull-ups (which tremendously reduces the quiescent current and makes CMOS perfect for digital logic). With CMOS it makes more sense to use the weaker PMOS (PNP) transistors in parallel for pull up and use the stronger NMOS (NPN) transistors in series for pull down and the natural configuration is the NAND gate.
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