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TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

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Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#61

Post by ineedasername »

baybal2 wrote: post #32
ksec wrote: post #25

Earlier quoted context omitted.

>I hope you're right, 5nm started risk production were direct from TSMC report. They are expecting even faster ramp than 7nm. And TSMC has a history of being very conservative. Their approach has been iteration rather than a leap like Intel did. And you can bet it will arrive on scheduled for next year's Apple iPhone. There are roadmap, tools, technique for 3nm ( As explained in the Article ) and even 2nm. So none of…

I bet yes, just the top dog clients will have to change. See, semiconductor companies might look like quite formidable, but the Internet companies like Facebook, Amazon, Google actually have more money then even them. They will pay. For consumer electronics, there is genuinely no benefits now going to smaller nodes, but for something like a "single chip supercomputer" type products, made with the most over the top se…

Wouldn't smaller nodes benefit consumer electronics with lower power consumption at similar performance? Better battery life, etc.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#62

Post by ComputerGuru »

ivalm wrote: post #41
vasili111 wrote: post #33

Earlier quoted context omitted.

What is the theoretical limit? I mean there should be end.

Current density is ~100M (1E8) transistors/mm^2, Assuming transistors with a side of ~10 atoms (and bond length 0.5nm) that means we could get ~4E12 transistors/mm^2. This is almost certainly over optimistic but still it shows that we are orders of magnitude away from limits due to "atomic nature" of matter.

I think you first need to switch to transistors/nm^3 rather than thinking only in 2d.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#63

Post by NortySpock »

ineedasername wrote: post #61
baybal2 wrote: post #32

Earlier quoted context omitted.

I bet yes, just the top dog clients will have to change. See, semiconductor companies might look like quite formidable, but the Internet companies like Facebook, Amazon, Google actually have more money then even them. They will pay. For consumer electronics, there is genuinely no benefits now going to smaller nodes, but for something like a "single chip supercomputer" type products, made with the most over the top se…

Wouldn't smaller nodes benefit consumer electronics with lower power consumption at similar performance? Better battery life, etc.

Yes, but I think the cost of the chip (and cost per transistor on the chip) is starting to go back up again with each die shrink, rather than down every die shrink.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#64

Post by dralley »

wmf wrote: post #21
agumonkey wrote: post #19

Earlier quoted context omitted.

btw, what happened to GF ?

GF canceled 7 nm; I guess they didn't have enough money to support the R&D needed to develop advanced processes.

They had already developed the node, or in any case, IBM had (and they purchased the IBM fab research division). But they didn't have the capital to scale out. They decided it would be more profitable and less risky to stay on 14nm and serve the long tail of customers that don't use leading edge nodes.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#65

Post by Dylan16807 »

sanxiyn wrote: post #10
simonebrunozzi wrote: post #9

I hate when acronyms prevent people from understanding important parts of an article. Here you go. TSMC = "Taiwan Semiconductor Manufacturing Company, Limited, also known as Taiwan Semiconductor, is the world's largest dedicated independent semiconductor foundry" (from Wikipedia).

You are expected to know what TSMC is if you are reading this... People wouldn't expand AMD to Advanced Micro Devices and then explain it develops CPU (Central Processing Unit, in case you didn't know!), would they?

You're expected to know what they are, but I couldn't have given you the full version of either. It's pretty irrelevant to the conversation, more trivia than anything.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#66

Post by AFascistWorld »

bitL wrote: post #58
ahartmetz wrote: post #44

Earlier quoted context omitted.

AMD was lucky, but it is also being run by a highly accomplished semiconductor physicist, so some things are perhaps a little less luck than one might think.

I would vote for Lisa to be the CEO of the year. It's also fun to know she is a relative of NVidia boss that once worked at AMD and they both are from Taiwan, home of TSMC and who knows if they have family inside as well...

No she's not his relative.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#67

Post by dumbfoundded »

wmf wrote: post #16
jsf01 wrote: post #14

This has me really excited for the future. One question I have now is how this compares to Intel’s roadmap. I’ve read comparisons like “TSMC 7nm is equivalent to Intel 10nm” but never seen any further discussion that goes deeper into how that’s true.

From the same site: https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells... Scroll down near the bottom.

To summarize the article: the density at which Intel can pack the transistors on a chip is high enough even with a larger transistor size, still means Intel has more transistors in the same chip size. The advantage of the 7nm TSMC transistor is that they are faster and more power-efficient.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#68

Post by 6nf »

geogra4 wrote: post #5
wmf wrote: post #4

Earlier quoted context omitted.

Yes, although there was an element of luck that Intel 10 nm failed at the same time that TSMC 7 nm came out smoothly. The opposite situation happened back at 32 nm and could happen again.

yeah but how many nm are left? There's a phsyical limit to transistor size!

5 left

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#69

Post by baybal2 »

ineedasername wrote: post #61
baybal2 wrote: post #32

Earlier quoted context omitted.

I bet yes, just the top dog clients will have to change. See, semiconductor companies might look like quite formidable, but the Internet companies like Facebook, Amazon, Google actually have more money then even them. They will pay. For consumer electronics, there is genuinely no benefits now going to smaller nodes, but for something like a "single chip supercomputer" type products, made with the most over the top se…

Wouldn't smaller nodes benefit consumer electronics with lower power consumption at similar performance? Better battery life, etc.

The performance of an individual transistor actually went down in 14>10>7 transition, but since you can pack more of them, the net effect is gain for companies with huge chips

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#70

Post by ivalm »

ComputerGuru wrote: post #62
ivalm wrote: post #41

Earlier quoted context omitted.

Current density is ~100M (1E8) transistors/mm^2, Assuming transistors with a side of ~10 atoms (and bond length 0.5nm) that means we could get ~4E12 transistors/mm^2. This is almost certainly over optimistic but still it shows that we are orders of magnitude away from limits due to "atomic nature" of matter.

I think you first need to switch to transistors/nm^3 rather than thinking only in 2d.

Right now these are planar devices. If you stack you can get orders of magnitude more. That's why you can get absurd memory capacities in things like nitrogen defect diamonds [0].

[0] https://advances.sciencemag.org/content/2/10/e1600911.full

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