PCI Express on the Raspberry Pi 4 • Hacker News Board

Re: PCI Express on the Raspberry Pi 4

#71

Post by bluecmd » Wed, Jul 10, 2019, 1:28 PM UTC

markus92 wrote: post #69

floatboth wrote: post #57

Earlier quoted context omitted.

VBIOS is often not necessary for running a GPU in the OS. The amdgpu driver can POST a GPU by itself just fine. Still… X86EmulatorPkg allows running an amd64 VBIOS in UEFI on an aarch64 machine :) AFAIK the bigger problem on embedded boards is half assed Synopsys Designware host controllers. I have a Radeon running on my Marvell MACCHIATObin, on FreeBSD even. But from what I've heard the Rockchip RK3399 has a worse v…

Could you clarify to me/give a short definition of BAR space? For obvious reasons it's a bit hard to search for :)

Search "PCIe bar space" and you should be fine

Re: PCI Express on the Raspberry Pi 4

#72

Post by buildbuildbuild » Wed, Jul 10, 2019, 1:29 PM UTC

Fun. If you want PCIe on a SBC without the soldering, I highly recommend perusing Hackerboards. I'm very happy with my RockPi 4 (4GB RAM, PCIe, USB 3, 6 cores), which I discovered through their excellent database.

https://www.hackerboards.com/search_boarddb.php

Re: PCI Express on the Raspberry Pi 4

#73

Post by Teknoman117 » Wed, Jul 10, 2019, 1:45 PM UTC

qdot_me wrote: post #6

Jonnax wrote: post #2

That's really cool. I'm curious, would it be possible to use a modern GPU (running at 1x) on an ARM based board? Would the open source drivers that are part of the Kernel work out the box on ARM?

Hack’s creator here - it’s on my list of things to try. GPUs are notoriously hard to get to work on non-intel, having tried to get a few up on Alpha and Itaniums in the past. VideoBIOS expects to run and expects a well behaving Intel CPU to do the power-up. That said X can sometimes emulate these quite well. On ARM we’d also run into alignment issues and likely other quirks - but in principle...

SiFive has a few videos where they have their RISC-V core running an AMD gpu (via the in kernel amdgpu driver).

Re: PCI Express on the Raspberry Pi 4

#74

Post by mallets » Wed, Jul 10, 2019, 1:46 PM UTC

I think I will wait for the pi 4 compute model, tyvm.

Re: PCI Express on the Raspberry Pi 4

#75

Post by wang_li » Wed, Jul 10, 2019, 1:47 PM UTC

Aren't PCIe lanes shared? Why would I need to remove the USB 3.0 chip rather than just hooking right to the pins on the device where it's soldered in place?

E: Apparently it's the PCI bus that is shared, not PCI Express lanes. Ty.

Re: PCI Express on the Raspberry Pi 4

#76

Post by megous » Wed, Jul 10, 2019, 1:55 PM UTC

londons_explore wrote: post #65

girvo wrote: post #56

Earlier quoted context omitted.

If I’m reading it right, don’t you give up USB to get this PCIe access?

Bet the broadcom SoC has a USB controller built in, but unused... You could hook it up?

https://lb.raspberrypi.org/documentation/hardware/raspberryp...

This says, there's OTG controller intended to be used in "peripheral device only" mode.

I haven't found datasheet for BCM2711, so it's hard to tell.

Re: PCI Express on the Raspberry Pi 4

#77

Post by blep-arsh » Wed, Jul 10, 2019, 1:57 PM UTC

wang_li wrote: post #75

Aren't PCIe lanes shared? Why would I need to remove the USB 3.0 chip rather than just hooking right to the pins on the device where it's soldered in place? E: Apparently it's the PCI bus that is shared, not PCI Express lanes. Ty.

Nope, point-to-point.

Re: PCI Express on the Raspberry Pi 4

#78

Post by londons_explore » Wed, Jul 10, 2019, 2:01 PM UTC

megous wrote: post #76

londons_explore wrote: post #65

Earlier quoted context omitted.

Bet the broadcom SoC has a USB controller built in, but unused... You could hook it up?

https://lb.raspberrypi.org/documentation/hardware/raspberryp... This says, there's OTG controller intended to be used in "peripheral device only" mode. I haven't found datasheet for BCM2711, so it's hard to tell.

> peripheral device only mode.

I wonder why? The silicon required is far far simpler for host mode (since you only need a single memory buffer, and you fully dictate the timing, so can pass all the complex stuff up to software).

Re: PCI Express on the Raspberry Pi 4

#79

Post by strmpnk » Wed, Jul 10, 2019, 2:02 PM UTC

wang_li wrote: post #75

Aren't PCIe lanes shared? Why would I need to remove the USB 3.0 chip rather than just hooking right to the pins on the device where it's soldered in place? E: Apparently it's the PCI bus that is shared, not PCI Express lanes. Ty.

AFAICT lanes are not shared but there are chipsets which can break lanes out into other sets of lanes which are then routed back onto the original set of lanes. So if your CPU has 16 lanes you can hang a chip off of it which then provides more lanes which are then signaled back to the CPU over some subset of those lanes.

It’s not clear if the lanes themselves can be multiplexed with packets from many devices but they can change the number of assigned lanes after initialization so a clever chipset could probably dynamically allocate lanes as used.

Re: PCI Express on the Raspberry Pi 4

#80

Post by Kirby64 » Wed, Jul 10, 2019, 2:08 PM UTC

wang_li wrote: post #75

Aren't PCIe lanes shared? Why would I need to remove the USB 3.0 chip rather than just hooking right to the pins on the device where it's soldered in place? E: Apparently it's the PCI bus that is shared, not PCI Express lanes. Ty.

Nope. PCIe lanes are not shared. There are some chips (and a lot of motherboards) that allow (or automatically perform) remapping of lanes, though. That's why if you check a motherboard with SLI/Crossfire, it usually has some setting in the BIOS to either dedicate all 16 lanes to 1 PCIe 16x slot or split 2 PCIe 16x slots 8 and 8.

The chip has to be removed.