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A Look at the AMD Zen 2 Core

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Re: A Look at the AMD Zen 2 Core

#71
post #42

Earlier quoted context omitted.

As far as I know, these processors are not yet released. What's the confidence level that this user benchmark will be indicative of real life expected performance? It seems implausible that this user benchmark is a good indicator. The Zen 1 architecture exhibited nothing of the sort[0] -- it would be an order of magnitude performance regression. I expect we'll start to see more accurate tests once the processors are…

https://images.anandtech.com/doci/14525/TravisK_DonW-Next_Ho... >69 ns at 3600C16

>67ns at 3733C17

I'd go for that.

Re: A Look at the AMD Zen 2 Core

#72
post #3

This isn't directly related to Zen 2 (sorry), but it's something I've been wondering about: How do processors that split ops into uops implement precise interrupts? I sort of understand how the ROB is used to implement precise interrupts even with pipelining and OOO, but I don't quite see how processors map uops back to the original instruction sequence.

I'd assume the simplest thing to do would be to flush the pipeline as if you had a branch mispredict, the interrupt can be delivered instead of an alternate branch target.

Re: A Look at the AMD Zen 2 Core

#73
post #23

Earlier quoted context omitted.

Well, to be devil's advocate: just because AMD improved their memory latency does not mean it was state-of-the-art. Indeed, looking at some random user benchmarks of Zen 1, it looks like the memory latency is similar with Zen 1. (See my reply to parent for a couple links, but I think you could also just find random Ryzen 2700X benches and see the same.) Of course, the effects of ~20ns more latency on system memory ac…

But Zen 2 has HUGE L3 cache. I think that this cache would compensate for that latency.

Actually, the L3 cache is also sharded across chiplets, so there's a small (~8MB) local portion of L3 that is fast, while remote slices will have to go over AMD's interdie connection fabric and incur a serious latency penalty. On first gen Epyc/Threadripper, nonlocal L3 hits were almost as slow as DRAM at ~100ns (!).

Re: A Look at the AMD Zen 2 Core

#75
post #40
post #18

Zen 2 is very good in number crunching and synthetics. But it has a problem - terrible memory latency. 70ns with 3600cl16. ( https://www.userbenchmark.com/UserRun/18168279 ) It distills to a not-so-good gaming frame times. It's 64mb L3 cache ( https://en.wikichip.org/wiki/amd/ryzen_9/3900x ) helps only partially. Few games will suffer greatly from it, but there are several titles with RAM bottlenecks, like PUBG and F…

That benchmark only has a few samples on an unreleased cpu. Typical ballpark numbers for memory latency are usually 100ns. There are also a lot of factors that can influence random memory access such as whether the lookup is going through virtual memory that isn't a page in the TLB cache. I'm skeptical this benchmark tells us much. Also games that are sensitive to memory latency are very poorly written games. This is…

PUBG runs on Unreal Engine[1], which obviously Epic used for Fortnite as well.

This inside relationship Epic had was the source for some of the erm friction between the two Battle Royale games.

1 - https://en.m.wikipedia.org/wiki/PlayerUnknown's_Battleground...

Re: A Look at the AMD Zen 2 Core

#76

Earlier quoted context omitted.

But Zen 2 has HUGE L3 cache. I think that this cache would compensate for that latency.

Actually, the L3 cache is also sharded across chiplets, so there's a small (~8MB) local portion of L3 that is fast, while remote slices will have to go over AMD's interdie connection fabric and incur a serious latency penalty. On first gen Epyc/Threadripper, nonlocal L3 hits were almost as slow as DRAM at ~100ns (!).

Does that local vs remote L3 show up in the NUMA information?

Re: A Look at the AMD Zen 2 Core

#77
post #71
post #42

Earlier quoted context omitted.

https://images.anandtech.com/doci/14525/TravisK_DonW-Next_Ho... >69 ns at 3600C16

>67ns at 3733C17 I'd go for that.

I was curious as to what Intel’s number’s look like. Found the 2nd gen Ryzen matched the random latency for the 7th gen i7, but while the 3rd gen at 3733CL17 gets 67ns, it’s 53-54 ns for the 8th and 9th gen i7/i9. So that’s narrowed to 13 ns slower, a 24% drop in performance (or a 20% improvement, depending on how you look at it...) While it does matter, we’re comparing 8 core parts to 12 core parts, so it’s possible that 50% more cores outweighs a 24% increase in memory latency, or alternatively that 33% fewer cores could hurt performance more than 20% faster memory latency. Ehh... it’s a mixed bag for me. I can see how increased memory latency hurts performance, and it’s unclear what the minimum random latency is at different CL settings and speeds on the Intel side. Also there’s a slight single digit ns penalty to sharing memory across units, a concept the comparable Intel parts don’t have, if I’m reading this right.

That said, the X570 chipset has PCIe 4.0 with improved power management to match, even at the ITX end. But PCIe 4 will likely go through implementation improvements and right now is only useful for storage in really fast Raid configurations, 15GB/sec performance from 4 drives has been demonstrated at a relatively cheap cost, comparable to high end commodity NVMe PCI 3 storage.

I wish it were obvious which part was “best” but different implementations lead to different optimizations/costs/benefits...

Re: A Look at the AMD Zen 2 Core

#78
post #55
post #3

This isn't directly related to Zen 2 (sorry), but it's something I've been wondering about: How do processors that split ops into uops implement precise interrupts? I sort of understand how the ROB is used to implement precise interrupts even with pipelining and OOO, but I don't quite see how processors map uops back to the original instruction sequence.

First, most uops can't throw exceptions, so fusing a shift and an add instruction together doesn't require any complex tracking here. If a uop throws an exception (let's say a fused add+ld), each uop can have a tag that helps you backtrace to its PC (instruction address) of let's say the start of the sequence, so you know what to inform the Privileged Architecture as to what "instruction" excepted. For many reasons,…

Instructions such as shift and add that have memory operands can throw exceptions on x86/amd64. (This was some of the motivations of RISC, separating loads/stores from ALU ops made exception handling cleaner).

Heh, random note, I just looked up shift instructions on x86, there are 6 different ones, not RISC. But today there's a lot over 1000 instructions so a few shift variants are peanuts.

Re: A Look at the AMD Zen 2 Core

#79
post #71

Earlier quoted context omitted.

>67ns at 3733C17 I'd go for that.

I was curious as to what Intel’s number’s look like. Found the 2nd gen Ryzen matched the random latency for the 7th gen i7, but while the 3rd gen at 3733CL17 gets 67ns, it’s 53-54 ns for the 8th and 9th gen i7/i9. So that’s narrowed to 13 ns slower, a 24% drop in performance (or a 20% improvement, depending on how you look at it...) While it does matter, we’re comparing 8 core parts to 12 core parts, so it’s possible…

A very interesting article is https://www.pcworld.com/article/3298859/how-memory-bandwidth... which brings up Linux vs Windows, and compares the slightly older ThreadRipper 2nd gen to the 7th gen i9 part. Which means it’s possible the i9 outperforms the Zen 2 parts still, if random access memory is required and you’re on Windows where the difference is more apparent...

Re: A Look at the AMD Zen 2 Core

#80
post #45
post #43

Earlier quoted context omitted.

2400 vs 3000 vs 3200 MHz RAM | Ryzen 2nd gen: https://youtu.be/TjMq-Nv6Mq8 It affects general tasks too, but with much less magnitude than gaming, because games are concerned with frame times and overall latency the most.

Well, sure... but doesn't increasing the RAM clock increase the throughput as well? What I'm asking is, is there a good way to test the effects of just memory latency?

Here is a fresh Zen1 timings comparison from Reddit[1].

Most increase is between 3200cl14 vs 3200cl12. 12%. Difference between this two is almost purely a Latency.

Then compare 3200cl12 and 3600cl14 - 3%, marginally no increase. Almost no difference in latency, only throughput and IF.

Past 3200 RAM throughput and inter-core-communication (IF) has very little influence for Zen1 gaming. For Zen2 this scenario would differ in some ways but not too much.

[1]: https://www.reddit.com/r/Amd/comments/c9x8v7/2700x_memory_sc...

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