"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary? Is this a gimmicky marketing term, or is it logical\descriptive\rational?
[deleted]
A Look at the AMD Zen 2 Core
11–20 of 94 posts
Re: A Look at the AMD Zen 2 Core
#12[deleted]
Re: A Look at the AMD Zen 2 Core
#13The post states: >"Perceptrons are the simplest form of machine learning and lend themselves to somewhat easier hardware implementations compared to some of the other machine learning algorithms." Can someone explain what is it about perceptrons that make them easier to implement in hardware?
There's a very approachable explanation in the following (around the 1:01:40 mark): https://youtu.be/8I_1TSs695I?t=1h1m40s -- part of Design of Digital Circuits - Lecture 18: Branch Prediction II (ETH Zürich, Spring 2019). Related readings: https://safari.ethz.ch/digitaltechnik/spring2019/doku.php?id....
These lectures are pretty great, by the way, highly recommended to anyone interested in computer architecture: http://people.inf.ethz.ch/omutlu/lecture-videos.html
Incidentally, this year's High-Performance Computer Architecture Test of Time Award has been given to "Dynamic Branch Prediction with Perceptrons" referenced in the lecture (from 2001, https://www.cs.utexas.edu/~lin/papers/hpca01.pdf): https://engineering.tamu.edu/news/2019/02/jimenez-receives-h....
Re: A Look at the AMD Zen 2 Core
#14"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary? Is this a gimmicky marketing term, or is it logical\descriptive\rational?
(Note: Also replied to another comment, but seems relevant here, too.)
There's a very approachable explanation in the following (around the 1:01:40 mark): https://youtu.be/8I_1TSs695I?t=1h1m40s -- part of Design of Digital Circuits - Lecture 18: Branch Prediction II (ETH Zürich, Spring 2019). Related readings: https://safari.ethz.ch/digitaltechnik/spring2019/doku.php?id....
These lectures are pretty great, by the way, highly recommended to anyone interested in computer architecture: http://people.inf.ethz.ch/omutlu/lecture-videos.html
Incidentally, this year's High-Performance Computer Architecture Test of Time Award has been given to "Dynamic Branch Prediction with Perceptrons" referenced in the lecture (from 2001, https://www.cs.utexas.edu/~lin/papers/hpca01.pdf): https://engineering.tamu.edu/news/2019/02/jimenez-receives-h....
Re: A Look at the AMD Zen 2 Core
#15This isn't directly related to Zen 2 (sorry), but it's something I've been wondering about: How do processors that split ops into uops implement precise interrupts? I sort of understand how the ROB is used to implement precise interrupts even with pipelining and OOO, but I don't quite see how processors map uops back to the original instruction sequence.
I'm not an expert but I believe what accomplishes this task is the reorder buffer. This allows the instruction execution and its side effects to be separated.
The parent's ROB is the reorder buffer. AIUI it causes the instructions to be retired in order (with exceptions stored until retirement, then exposed). The original question, though is how a particular u-op is mapped back to the original macro-instruction, so we know what macro-instruction excepted.
And I don't know. I guess is if each u-op is tagged with the instruction address within the process, that would do, but that's carrying around at least 32 bits, which is quite a large tag.
Alternatively tag indirectly, which is more likely (you can have maybe 256 instructions 'hot' at any time so an 8-bit tag on each u-op pointing to a 32 or 64-bit table entry (edit: holding the actual address of the macro-op). And the window for the ROB and the other thing that does instruction issue, is ~200 instructions, so that sounds more plausible).
All speculation on my part though!
Re: A Look at the AMD Zen 2 Core
#16Earlier quoted context omitted.
I'm not an expert but I believe what accomplishes this task is the reorder buffer. This allows the instruction execution and its side effects to be separated.
The parent's ROB is the reorder buffer. AIUI it causes the instructions to be retired in order (with exceptions stored until retirement, then exposed). The original question, though is how a particular u-op is mapped back to the original macro-instruction, so we know what macro-instruction excepted. And I don't know. I guess is if each u-op is tagged with the instruction address within the process, that would do, but…
I see what they mean then. I read the question a bit too fast.
I was mostly assuming that the issue of the operation reserved a spot in the outstanding buffer which would ensure sequencing of the write or commit after execution which would walk through the buffer in sequence.
But you're right that there are still more questions to how some of that data is tracked through the pipeline.
Re: A Look at the AMD Zen 2 Core
#17The post states: >"Perceptrons are the simplest form of machine learning and lend themselves to somewhat easier hardware implementations compared to some of the other machine learning algorithms." Can someone explain what is it about perceptrons that make them easier to implement in hardware?
Wait, how is K-NN harder to implement than a perception... Even in hardware? What about linear regression? What about decision trees? What about naive Bayes?
Re: A Look at the AMD Zen 2 Core
#18Zen 2 is very good in number crunching and synthetics. But it has a problem - terrible memory latency. 70ns with 3600cl16. (https://www.userbenchmark.com/UserRun/18168279) It distills to a not-so-good gaming frame times. It's 64mb L3 cache (https://en.wikichip.org/wiki/amd/ryzen_9/3900x) helps only partially.
Few games will suffer greatly from it, but there are several titles with RAM bottlenecks, like PUBG and FarCry.
Anyway, AMD has a much better price/performance offer than Intel. For general puprose Intel is totaly anihilated, but for the games they are still more than competitive.
Re: A Look at the AMD Zen 2 Core
#19Earlier quoted context omitted.
I'm not an expert but I believe what accomplishes this task is the reorder buffer. This allows the instruction execution and its side effects to be separated.
The parent's ROB is the reorder buffer. AIUI it causes the instructions to be retired in order (with exceptions stored until retirement, then exposed). The original question, though is how a particular u-op is mapped back to the original macro-instruction, so we know what macro-instruction excepted. And I don't know. I guess is if each u-op is tagged with the instruction address within the process, that would do, but…
Perhaps there are two copies of the program pointer, one at the "top of the pipe" updated by instruction decode and branch prediction, and one at the "bottom of the pipe" updated by the ROB. Then uops only need to carry the amount by which the program counter is advanced, and certain events can cause a pipeline flush and copy the bottom of pipe version of the counter to the top of the pipe.
But that's also all speculation :)
Re: A Look at the AMD Zen 2 Core
#20Zen 2 is very good in number crunching and synthetics. But it has a problem - terrible memory latency. 70ns with 3600cl16. ( https://www.userbenchmark.com/UserRun/18168279 ) It distills to a not-so-good gaming frame times. It's 64mb L3 cache ( https://en.wikichip.org/wiki/amd/ryzen_9/3900x ) helps only partially. Few games will suffer greatly from it, but there are several titles with RAM bottlenecks, like PUBG and F…
As far as I know, these processors are not yet released. What's the confidence level that this user benchmark will be indicative of real life expected performance?
It seems implausible that this user benchmark is a good indicator. The Zen 1 architecture exhibited nothing of the sort[0] -- it would be an order of magnitude performance regression.
I expect we'll start to see more accurate tests once the processors are actually released into the wild.
[0]https://www.tomshardware.com/reviews/amd-ryzen-7-2700x-revie...