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MIPS R3000

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Re: MIPS R3000

#41

Post by monocasa »

snvzz wrote: post #27
monocasa wrote: post #22

Earlier quoted context omitted.

Check out the Apollo Core. FPGA soft core for an out of order 68k that they call a 68080. Even in an FPGA it's faster than any released 68k. http://www.apollo-core.com/

I'm somewhat familiar with the Apollo Core, as I own a V500v2+. It's amazing; Too bad it's not open source. There's some open source 68000 implementations, but they're all still slow. The most well-known is perhaps tg68k, used in MiSTer cores and in FPGA Arcade.

Yeah, I've got a pipe dream of taking BOOM and strapping a 68k decoder frontend to it too. Like the PowerPC 615, but RISC-V/68k instead of PowerPC/x86.

Re: MIPS R3000

#42

Post by jawnv6 »

x0re4x wrote: post #9
mepian wrote: post #7

Earlier quoted context omitted.

How annoying were the branch delay slots?

You could always put NOPs into delay slots by default and replace them later with something more useful.

no, you could not "always" find something useful to put there later. gross exaggeration

Re: MIPS R3000

#43

Post by monocasa »

kristopolous wrote: post #36
monocasa wrote: post #21

Earlier quoted context omitted.

Alpha is bae. PowerPC is great as long as you don't look at the fever dream nightmare that is it's supervisor state.

Want one? I've got a 600mhz sitting in the cost. Totally works. I'm in Los Angeles

Haha, my partner would be unhappy if I came home with another stray, but I appreciate the offer. : )

Re: MIPS R3000

#44

Post by pjc50 »

snvzz wrote: post #6
segfaultbuserr wrote: post #3

Alternative history time: what if MIPS R4000 hasn't been killed by Pentium? Would we be running R10000-compatibles now?

Even more fun alternative history: What if Motorola didn't end 68000 with the 68060? 68060 released earlier than the pentium, and regardless it had about twice the performance per clock. But then Motorola decided to abandon 68k to focus on PowerPC. Going further back: What if IBM picked 68000 over the 8086 for the PC? I'm hoping RISC-V will put an end to x86. It's about time.

> I'm hoping RISC-V will put an end to x86. It's about time.

Not only is this wishful thinking and ignores the success so far of ARM, it doesn't make much sense any more - x86 is already "dead", almost all modern PCs will run amd64, with x86 as a kind of short-instruction emulation mode.

Re: MIPS R3000

#45

Post by mrguyorama »

jawnv6 wrote: post #42
x0re4x wrote: post #9

Earlier quoted context omitted.

You could always put NOPs into delay slots by default and replace them later with something more useful.

no, you could not "always" find something useful to put there later. gross exaggeration

You misunderstood parent. They meant you can always nop the branch delay, and you might find something more useful for it later

Re: MIPS R3000

#46

Post by opencl »

cwt137 wrote: post #19

I remember reading a computer architecture book that used a fictional MIPS instruction set and used washing and drying clothes as an example of how to pipeline / do parallel instructions. Does anyone remember the name of that book?

That description probably applies to several computer architecture books, but the one I read was like that and called "Computer Organization and Design: The Hardware/Software Interface".

Re: MIPS R3000

#47

Post by gomijacogeo »

AnaniasAnanas wrote: post #30
opencl wrote: post #5

MIPS is a fun architecture (other than the delay slots that plagued early RISC ISAs) and implementing a subset of it on an FPGA is still a pretty common undergraduate university course project. I was kind of amazed just how simple it is to get a basic CPU working, though even the 1988 version was quite a lot more sophisticated than the class project version (multiple cache levels, having an MMU, probably much better…

Why does everyone seem to hate delay slots? I understand that it makes writing assembly more annoying but most people use a compiler anyway.

There was one nifty thing that fell out from having delay slots - you could write a threading library without having to burn a register on the ABI. When you changed context to a different thread, you'd load in all the registers for the new thread except for one which held the jump address to the new thread's IP. Then, in that jump's delay slot, you load in the thread's value for that register and, presto, zero overhead threading!

Re: MIPS R3000

#48

Post by kristopolous »

monocasa wrote: post #43
kristopolous wrote: post #36

Earlier quoted context omitted.

Want one? I've got a 600mhz sitting in the cost. Totally works. I'm in Los Angeles

Haha, my partner would be unhappy if I came home with another stray, but I appreciate the offer. : )

Hrmm. I could do a login if you really want. I have an openvms and netbsd disk.

I've been trying to not take this thing to ewaste for a decade

Re: MIPS R3000

#49

Post by jawnv6 »

mrguyorama wrote: post #45
jawnv6 wrote: post #42

Earlier quoted context omitted.

no, you could not "always" find something useful to put there later. gross exaggeration

You misunderstood parent. They meant you can always nop the branch delay, and you might find something more useful for it later

that may have been what they wanted to write. unfortunately they wrote something wrong and misleading instead. i understood what they wrote perfectly well and the implication therein isn't, somehow, my fault

Re: MIPS R3000

#50

Post by mrguyorama »

jawnv6 wrote: post #49
mrguyorama wrote: post #45

Earlier quoted context omitted.

You misunderstood parent. They meant you can always nop the branch delay, and you might find something more useful for it later

that may have been what they wanted to write. unfortunately they wrote something wrong and misleading instead. i understood what they wrote perfectly well and the implication therein isn't, somehow, my fault

The "always" qualifier does not apply to anything after the "and". Why do you assume it does? You are being very combative and pedantic so I assume you have a diehard rule for this that you can reference? Like some english grammar handbook?
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