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During my short experience with hardware design at the university I never had the chance of using Verilog. Are there advantages in using it instead of VHDL?
1) Less verbose and easier to write, but slightly more "error" prone (think: Java vs. Python).
2) More widely used in industry. VHDL is more heavily used in the defense industry (it came out of DoD).
3) Better support for verification (e.g., SystemVerilog).
During my short experience with hardware design at the university I never had the chance of using Verilog. Are there advantages in using it instead of VHDL?
VHDL only has GHDL. And there's a bunch of small projects to translate synthesizable VHDL into Verilog (to then feed into the aforementioned tooling), but none of them are good.
One cool thing you can do with Verilator is use the API to simulate other hardware. For example, here's a Verilog Gameboy being simulated realtime by simulating the display attached to it: https://twitter.com/zephray_wenting/status/11126917323936645...
Does anyone have links to free analog design tools?
Former: LTSpice (also runs under wine).
Latter: ngspice
Verilator has some serious limitations: The driving test bench is C/C++ It is a cycle simulator, not a delta-time simulator: it will only simulate synthesizable code (not test bench code) It cannot do back-annotated timing simulations It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example) It has no mixed-HDL language capabilities It requires Gtkwave to view waveforms with (opinion, but…
It dumps a value-change file (vcd) which can be viewed by anything, no? Sure it's not very compressed (and the compile-time for vcd-generation is unfortunate), but it's not a show-stopper.
Verilator has some serious limitations: The driving test bench is C/C++ It is a cycle simulator, not a delta-time simulator: it will only simulate synthesizable code (not test bench code) It cannot do back-annotated timing simulations It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example) It has no mixed-HDL language capabilities It requires Gtkwave to view waveforms with (opinion, but…
> It requires Gtkwave to view waveforms with (opinion, but I hate the UI) It dumps a value-change file (vcd) which can be viewed by anything, no? Sure it's not very compressed (and the compile-time for vcd-generation is unfortunate), but it's not a show-stopper.
I would be exceedingly happy to find one, however; please let me know.
Verilator has some serious limitations: The driving test bench is C/C++ It is a cycle simulator, not a delta-time simulator: it will only simulate synthesizable code (not test bench code) It cannot do back-annotated timing simulations It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example) It has no mixed-HDL language capabilities It requires Gtkwave to view waveforms with (opinion, but…
The first two are a feature for me. Not to mention not being crippled by Xilinx 'IP Core' DRM.
Is it perfect? Hell no. But it's a bit drastic to throw out an entire catalog of the most battle-tested HDL code in the world, isn't it?