Verilator: Fast, Free Verilog HDL Simulator
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Verilator: Fast, Free Verilog HDL Simulator
1–10 of 20 posts
Re: Verilator: Fast, Free Verilog HDL Simulator
#2Verilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a place-and-route tool. The set of these provide a pretty reasonable set of tools for developing hardware (that is HDL) with fully open source software!
[1] - http://iverilog.icarus.com/ [2] - http://www.clifford.at/yosys/ [3] - https://github.com/YosysHQ/nextpnr
Re: Verilator: Fast, Free Verilog HDL Simulator
#3And how does one get a cheap FPGA board out of it? China? Any recommendations?
Re: Verilator: Fast, Free Verilog HDL Simulator
#4Verilator has some serious limitations:
The driving test bench is C/C++
It is a cycle simulator, not a delta-time simulator: it will
only simulate synthesizable code (not test bench code)
It cannot do back-annotated timing simulations
It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example)
It has no mixed-HDL language capabilities
It requires Gtkwave to view waveforms with (opinion, but I hate the UI)
Re: Verilator: Fast, Free Verilog HDL Simulator
#5One cool thing you can do with Verilator is use the API to simulate other hardware. For example, here's a Verilog Gameboy being simulated realtime by simulating the display attached to it: https://twitter.com/zephray_wenting/status/11126917323936645...
Re: Verilator: Fast, Free Verilog HDL Simulator
#6And how does one get a cheap FPGA board out of it? China? Any recommendations?
Verilator is only a simulator, once you want to run it on a fpga you use yosys + nextpnr. The icestick is a popular and cheap choice to get started, there is also the TinyFPGA BX and iCEBreaker if you would like a few more features.
Re: Verilator: Fast, Free Verilog HDL Simulator
#7Verilator has some serious limitations: The driving test bench is C/C++ It is a cycle simulator, not a delta-time simulator: it will only simulate synthesizable code (not test bench code) It cannot do back-annotated timing simulations It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example) It has no mixed-HDL language capabilities It requires Gtkwave to view waveforms with (opinion, but…
It has a steep learning curve, but overall I think it forces you to adopt good development practices from the start. Since it generates C++ you can also easily wrap that code and expose it to python. That way you can use software tools instead of system verilog and can easily do integration testing with your software HAL. In practice our group uses commercial tools (synopsis, cadence) and DPI-C but for the most part this is because of the VHDL code we have. Vivado‘s build in simulator is way too slow.
Re: Verilator: Fast, Free Verilog HDL Simulator
#8Verilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a place-and-route tool. The set of these provide a pretty reasonable set of tools for developing hardware (that is HDL) with fully open source software! [1] - http://iverilog.icarus.com/ [2] -…
There's a longer curated list of general HDL languages and tools here: https://github.com/drom/awesome-hdl
Re: Verilator: Fast, Free Verilog HDL Simulator
#9Verilator has some serious limitations: The driving test bench is C/C++ It is a cycle simulator, not a delta-time simulator: it will only simulate synthesizable code (not test bench code) It cannot do back-annotated timing simulations It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example) It has no mixed-HDL language capabilities It requires Gtkwave to view waveforms with (opinion, but…
The first two are a feature for me. Not to mention not being crippled by Xilinx 'IP Core' DRM.
Re: Verilator: Fast, Free Verilog HDL Simulator
#10During my short experience with hardware design at the university I never had the chance of using Verilog. Are there advantages in using it instead of VHDL?