Earlier quoted context omitted.
Your comment is extremely confused. Let's unpack some of the confusion... > NVIDIA’s scalar architecture NVidia doesn't have a scalar architecture in any meaningful sense of the word. Individual work items execute in warps, meaning (up to) 32 items execute the same instruction, at the same PC. If you have divergence, i.e. fewer than 32 items at the same instruction, you lose ALU throughput. This is the same as in AMD…
> NVidia doesn't have a scalar architecture in any meaningful sense of the word. While I agree with your post in general, I'm not totally in agreement here. If you look at the context in which G80 and CUDA were introduced, it has a significant scalar dimension: for a single "thread" writing an addition between two float3 ended up being executed as 3 separate additions on the scalar components of the vector. This was,…
If you look at the actual hardware, though, they're clearly both vector architectures: each "core" has N SIMD-style lanes executing the same instruction simultaneously; it's just that each of those lanes corresponds to a different work item of the compute dispatch.
This applies equally to AMD's and Nvidia's architectures.