Your comment is
extremely confused. Let's unpack some of the confusion...
> NVIDIA’s scalar architecture
NVidia doesn't have a scalar architecture in any meaningful sense of the word. Individual work items execute in warps, meaning (up to) 32 items execute the same instruction, at the same PC. If you have divergence, i.e. fewer than 32 items at the same instruction, you lose ALU throughput. This is the same as in AMD (and every other GPU architecture out there, for that matter).
The difference to AMD's architecture since Volta is that there is hardware support for each SIMD lane having its own PC, which makes it easier to have independent forward progress and a bunch of other features. The separate lanes don't have separate instruction fetch, though -- they all execute the same instruction (and if they can't, then some lanes will be disabled).
> this is why “async” compute doesn’t benefit them as much as it does GCN cards
Nvidia literally cannot do async compute in the same way as AMD, because their micro-architecture cannot switch between graphics and compute on as finely grained a basis as GCN cards. That's why they don't benefit from async compute. (Though I'm not sure whether that's still true since Volta.)
> GCN cards that have a 4 wide SIMD array
GCN has 64-wide waves, though with a bit of a weird execution scheduling which means that 16 lanes out of the 64 are computing at a time. Nowhere in GCN are there any 4-wide SIMD arrays.
> a massive external compute scheduler that sits idle when doing graphics.
Also nonsense. Both AMD and Nvidia have the majority of die space allocated to the compute cores (whatever they're calling them). The pieces of fixed function logic that distribute work onto the cores (whether for graphics or compute) are comparatively tiny.