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AMD Discloses Initial Zen 2 Details

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Re: AMD Discloses Initial Zen 2 Details

#171

Post by Tuna-Fish »

Const-me wrote: post #95

> meaning 256-bit AVX operations no longer need to be cracked into two 128-bit micro-ops per instruction The instruction set stayed the same. And in the current instruction set, a lot of these AVX instruction still operate on 128 bit lanes. Instructions like vpshufd, vshufps, vpblendw only shuffle/blend/permute within 128-bit lanes, so do AVX512 equivalents.

Yes, but that was not what the article was referring to. Zen1 CPUs only have 128-bit FPU lanes, and execute wider instructions by splitting them into two in the frontend.

Re: AMD Discloses Initial Zen 2 Details

#172

Post by gmueckl »

saiya-jin wrote: post #160
gmueckl wrote: post #142

Earlier quoted context omitted.

The hardware raytracing support is a huge step in the right direction for real time graphics. The shaky jenga tower of hacks on top of the rasterization pipeline that is in the current generation of rendering engines is barely sustainable. Fast raytracing provides an alternative that is much closer to the actual physical model of light transport in the real world and does not require as many nasty approximations and…

For a gamer, Nvidia's latest card offering is vastly disappointing. Technology that is not there and won't be there for maybe next 6 years (if they stick to 3 year release cycle), offering some shiny surfaces at best, at massively increased price. I really hope AMD will come with some good cheaper competition. Gamers want fast framerates, high polygon count, high textures much more than some currently-useless raytrac…

I don't get the ridiculous pricing of the current generation of nVidia chips, either. But this generation of hardware is at the same time an important step towards getting rendering algorithms that have vastly superior quality while having a much simpler structure. I know that anybody that works on high quality real time renderers and knows what they are doing wants this switch to happen.

Re: AMD Discloses Initial Zen 2 Details

#173

Post by Already__Taken »

ploek wrote: post #163
bpye wrote: post #64

Earlier quoted context omitted.

Asrock have been good in my experience at enabling all features on their boards. Back when Intel's Vt-d support depended on your board they reliably had support, and I believe they support ECC on all their new AMD boards.

I have ECC working on an AB350M Pro4. See also https://www.hardwarecanucks.com/forum/hardware-canucks-revie... The 'edac_mce_amd' module needs to be loaded on Linux.

I have one too, seems to be trucking along fine.

Re: AMD Discloses Initial Zen 2 Details

#174

Post by drewg123 »

Dylan16807 wrote: post #143
drewg123 wrote: post #36

Earlier quoted context omitted.

They are direct to 1/2 of the CPUs, actually. This is part of what the GP was complaining about. The 2 dies which do not have memory also do not have PCIe wired out of the socket, so they are one hop away from I/O as well. If you are trying to max out I/O, you'd probably be better off with a low-end Epyc that had fewer cores enabled per die. It is interesting to note that the memoryless dies do have PCIe root ports,…

The interconnect latencies give you something like an extra 50 nanoseconds[1]. That matters when accessing memory. Not so much for PCIe, where your base latency is most of a microsecond[2][3]. There seems to be plenty of bandwidth to handle it, too. [1] https://www.servethehome.com/amd-epyc-infinity-fabric-latenc... [2] https://forum.stanford.edu/events/posterslides/LowLatencyNet... [3] https://gianniantichi.github.i…

My comment was addressing the parent comment about bandwidth, not latency.

Because you only have 1/2 the memory and I/O bandwidth on threadripper, if maxing out I/O is your concern, you would likely be better off with a low-end epyc that still had all the memory controllers and pcie lanes wired up.

Re: AMD Discloses Initial Zen 2 Details

#175

Post by tutanchamun »

baybal2 wrote: post #35

Are there any more concrete proofs for the HBM2 on package possibility?

Do you mean the comment under the article that mentions HBM? If so I think they refer to these papers by AMD:

https://www.computermachines.org/joe/publications/pdfs/hpca2...

https://seal.ece.ucsb.edu/sites/seal.ece.ucsb.edu/files/publ...

Re: AMD Discloses Initial Zen 2 Details

#176

Post by dragontamer »

m_mueller wrote: post #147
piinbinary wrote: post #49

Does 1.25x performance at the same power refer to clock speed? Does that mean that we can expect 5 Ghz in Ryzen 3000?

Look up Dennard Scaling and how it broke.

Dennard Scaling would have been 2x clock-rate from an improved node.

1.25x scaling from an improved node is way, way, way worse than Dennard Scaling of the past.

Intel Pentium III Coppermine (1999) went from 733 MHz on the 180nm node to Pentium III Tualatin (2001) 1400 MHz on the 130nm node. THAT was Dennard scaling.

Today, we "only" get double-digit gains from an improved process node. Dennard Scaling was triple-digit gains. Furthermore, most CPU makers focus on the power-saving aspects (which seem to be scaling somewhat well still).

Re: AMD Discloses Initial Zen 2 Details

#177

Post by m_mueller »

dragontamer wrote: post #176
m_mueller wrote: post #147

Earlier quoted context omitted.

Look up Dennard Scaling and how it broke.

Dennard Scaling would have been 2x clock-rate from an improved node. 1.25x scaling from an improved node is way, way, way worse than Dennard Scaling of the past. Intel Pentium III Coppermine (1999) went from 733 MHz on the 180nm node to Pentium III Tualatin (2001) 1400 MHz on the 130nm node. THAT was Dennard scaling. Today, we "only" get double-digit gains from an improved process node. Dennard Scaling was triple-dig…

If you look at GP's question, (s)he was asking about 5Ghz in Zen2. Since Epyc 1 is ~3Ghz, a 1.6x increase in clock speed for a ~1.4x smaller process size (AFAIK "7nm" is overselling it compared to 14nm) to me smells like Dennard scaling and thus cannot be expected anymore (if you disregard tricks like turbo boost where a bunch of hardware gets disabled such that the rest can be boosted).

Re: AMD Discloses Initial Zen 2 Details

#178

Post by Symmetry »

tutanchamun wrote: post #157
zymhan wrote: post #96

Earlier quoted context omitted.

I was actually underwhelmed by the post, what exactly is the "pretty bold" change?

Seperating the analog logic (IO die) from the digital logic (CPU cores). Analog shrinks really bad with smaller nodes wheras digital logic shrinks really good. New process nodes get more and more expensive - especially if the node is new (bad yields etc.) So you want to get the most out of it as possible, which AMD does with this strategy. For example Zen 1 8 core chips are 213 mm2 on 14nm. On 7nm these chipse would…

There's also the clever business reason where they're obligated to keep buying silicon from Global Foundaries but GF had bowed out of pursuing 7nm. So here they can use GF's 14nm for enough silicon to cover their obligations.

Re: AMD Discloses Initial Zen 2 Details

#179

Post by blattimwind »

snuxoll wrote: post #59
blattimwind wrote: post #22

Earlier quoted context omitted.

2011-1 systems really aren't that power efficient. 16 DIMMs, 2 sockets will draw ~120 W idle .

Don’t populate all 16 DIMM’s unless you need that much memory? Both my single-socket R320 and dual-socket R520 idle at 70W each with 6 DIMM’s installed. Most people probably don’t need the gobs of memory I have either. A R520 with one socket populated and 2x8 or 16GB dual-ranked RDIMM’s would be more than sufficient.

I actually misspoke. The system above was configured with only 8 DIMMs (8 GB each) at the time. That's the lower limit for this platform before performance is degraded.

Re: AMD Discloses Initial Zen 2 Details

#180

Post by rasz »

ploek wrote: post #162
tutanchamun wrote: post #157

Earlier quoted context omitted.

Seperating the analog logic (IO die) from the digital logic (CPU cores). Analog shrinks really bad with smaller nodes wheras digital logic shrinks really good. New process nodes get more and more expensive - especially if the node is new (bad yields etc.) So you want to get the most out of it as possible, which AMD does with this strategy. For example Zen 1 8 core chips are 213 mm2 on 14nm. On 7nm these chipse would…

There is nothing analog about the IO die. It interfaces the memory, and the system's busses like PCIe. They are all digital.

its all analog at that level
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