81–90 of 114 posts
Sorry to burst any bubbles here, but this is s very incomplete implementation. You couldn’t run anything but small toy programs on this machine. This is more like what a student would build in an undergraduate course in computer architecture. For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc. Of course, one wouldn’t…
And with this https://bellard.org/riscvemu/ and similar projects already spun up in other ways, risc-v is becoming more interesting as time goes by.
Sorry to burst any bubbles here, but this is s very incomplete implementation. You couldn’t run anything but small toy programs on this machine. This is more like what a student would build in an undergraduate course in computer architecture. For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc. Of course, one wouldn’t…
Sorry to burst any bubbles here, but this is s very incomplete implementation. You couldn’t run anything but small toy programs on this machine. This is more like what a student would build in an undergraduate course in computer architecture. For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc. Of course, one wouldn’t…
That class was one of my favorites at UT. I was lucky enough to have a guy from Intel teach it as an adjunct.
Earlier quoted context omitted.
"Modern" desktop computing is perhaps less resource hungry than you think when you cut away so much graft of telemetry. None or barely few games, of course. But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text? I think it's very achievable.
> pure HTML browsing without javascript I highly doubt this is achievable now. Turn on NoScript and vast majority of web sites just refuse to work not even properly, but to just load the content.
The sites that need it are a small whitelist of ones I trust (e.g. the banks a sibling comment mentioned), which I enable.
...That said, a 75MHz RISC-V will be approximately comparable in performance to a 100MHz 486DX4, or a 40MHz Pentium.
Earlier quoted context omitted.
"Modern" desktop computing is perhaps less resource hungry than you think when you cut away so much graft of telemetry. None or barely few games, of course. But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text? I think it's very achievable.
It isn't the telemetry that's slowing us down, but layers upon layers of (mostly needless) abstraction and buffer bloat. Windows 95 had most of the things we use in a GUI environment today and it ran on a 486 with 8MB of ram. When packaged in Electron with a javascript x86 emulator it is still smaller than many modern text editors. Plenty of GUIs ran on significantly less. Since the modern web is basically one of the…
Earlier quoted context omitted.
That class was one of my favorites at UT. I was lucky enough to have a guy from Intel teach it as an adjunct.
What book did you use?
Earlier quoted context omitted.
Motorola assembler is what is known as orthogonal instruction set. The flow is logical: move.b for byte, move.w for word, move.l for longword, from source to destination, which reflects real life. The assembler reads almost like a high level programming language. The register scheme is intuitive as well, from a0-a7 being the address, to d0-d7 being the data registers. Now, let's do a mental exercise: I'm going to loa…
Indeed, in RISC-V, full 32-bit constants must be broken across two instructions. The translation goes: ; 1. lea MemoryAddress(pc), a0 auipc a0, [upper 20 bits of (MemoryAddress - label)] addi a0, a0, [lower 12 bits of (MemoryAddress - label)] label: ; 2. move.l #$00bfe001, a1 lui a1, 0x00bfe000 addi a1, a1, 0x001 ; 3. rts jalr x0, x1, 0 It is cumbersome in that sense. But it will probably be handled by an assembler (…
Any RISC processor has that issue, because encoding is fixed at 32-bits to keep the hardware simple. That's not what I'm referring to.
Look at that retardation, "auipc". Because "auipc" is intuitive, right? (For the record, I'm being sarcastic.) What the hell was the instruction designer smoking? Then there is the square bracket notation, like on intel, and intel has some of the most idiotic, non-conventional assembler syntax -- and this thing mimics something so bad? Every other processor uses parenthesis, that's a well understood norm.
Then there is more intel retardation in the form of dst, src (or dst, src, src on RISC). What kind of a warped, twisted mind came up with that? What was going on in that person's head to work in such twisted ways?
Then there's the "cherry on top":
jalr x0, x1, 0 ; because "jalr" is intuitive as well, it immediately tells you what it does?
Sorry to burst any bubbles here, but this is s very incomplete implementation. You couldn’t run anything but small toy programs on this machine. This is more like what a student would build in an undergraduate course in computer architecture. For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc. Of course, one wouldn’t…