Why Use an FPGA Instead of a CPU or GPU?
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Why Use an FPGA Instead of a CPU or GPU?
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Re: Why Use an FPGA Instead of a CPU or GPU?
#2Re: Why Use an FPGA Instead of a CPU or GPU?
#3Re: Why Use an FPGA Instead of a CPU or GPU?
#4Is there high performance FPGA that does not depend on proprietary bloated windows-only toolchain?
Re: Why Use an FPGA Instead of a CPU or GPU?
#5After some experience with FPGAs, the emulation step is not enough to test for correctness. Most of the problems happen while synchronizing signals with inputs/outputs and with other weird timing problems, glitches and unintuitive behavior that FPGAs provide (and the emulator behaves differently). I was using VHDL however. Anybody has experience with OpenCL on FPGAs to explain what difficulties persist (are the timing problems easier to solve)?
Re: Why Use an FPGA Instead of a CPU or GPU?
#6Is there high performance FPGA that does not depend on proprietary bloated windows-only toolchain?
Re: Why Use an FPGA Instead of a CPU or GPU?
#7Is there high performance FPGA that does not depend on proprietary bloated windows-only toolchain?
Re: Why Use an FPGA Instead of a CPU or GPU?
#8Is there high performance FPGA that does not depend on proprietary bloated windows-only toolchain?
Re: Why Use an FPGA Instead of a CPU or GPU?
#9Re: Why Use an FPGA Instead of a CPU or GPU?
#10"Intel does offer an emulator, so testing for correctness does not require this long step, but determining and optimizing performance does require these overnight compile phases." After some experience with FPGAs, the emulation step is not enough to test for correctness. Most of the problems happen while synchronizing signals with inputs/outputs and with other weird timing problems, glitches and unintuitive behavior…
A second more serious issue is that getting performance that justifies using an FPGA requires tuning very carefully to the architecture. This may mean adopting pipeline architectures that destroy emulator performance (there's still issues with the emulator identifying that the design patterns for shift registers in FPGA look like pointer fun on CPU rather than mammoth memcpys). So for a huge part of the design stage the emulator is basically useless- because it tells you nothing about what you care about, since the performance of the emulator is often negatively correlated with performance on FPGA. This is made worse if you're doing hardcore FPGA tricks like mixed precision arithmetic.
As you say though - the fact that timing is lost in the emulator also means you don't get a true idea of whether you have buffer overflows etc or lock-up. Adding debug into the actual design impacts the implementation on FPGA in a way that it doesn't for software - and is sometimes unintuitive.