Ahh Tilera. When MIT's RAW architecture went commercial and became Tilera, it looked like the multicore future was finally coming. They had a lot of nice devtools, like an eclipse-based simulator that let you visualize what was going on in the chip. 64 cores was really appealing, but because they didn't have floating point in the first set of chips, people mainly used them for network processing. Then.. Intel started…
You seem to know a lot. Any nice startups in this space?
I've found the 64x18b word limitation of memory per computer much less daunting than I did at the beginning, simply because how amazingly terse you can make your code. You also end up just simplifying, making your look-up-table or other array 8 or 16 words long...sometimes 32 or 64, but that's a bit more work.
One experiment I've done with it is harnessing 95 simultaneous cores for a virus vat, with a 47 core vat enclosure keeping it from hanging. The last 2 nodes are I/O and the probe to see what's going on. The virus is exactly one 18b word.