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The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

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Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#11

Post by qaute »

hinkley wrote: post #8

What stops us from wrapping the circuits around the sides of the chip? Holding onto them? Or the fact that stacking gets you more layers than 2 1/2?

It's a manufacturing limitation. Integrated circuits are nearly universally built via photolithography [1], which only makes flat 2D layers. Stacking many, many layers for 3D circuits is feasible; building layers on different sides of an object would require re-engineering every part of the process, including the use of large silicon wafers, for a much more complex process with negligible (if any) benefit.

[1] https://en.wikipedia.org/wiki/Photolithography#Basic_procedu...

edit: kragormonkey beat me to it!

Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#12

Post by Hasz »

deepnotderp wrote: post #5
agumonkey wrote: post #4

Earlier quoted context omitted.

people mention terrible heat dissipation in 3D, do they allocate thermal vias between the layers?

Yes, although this can be an extra challenge in monolithic 3D because it often involves oxide layers and thin silicon * between transistor layers, which makes the heat conduction much worse. *due to violation of Fourier theory of heat.

How difficult would it be to replace current oxide layers with something like BeO?

Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#13

Post by deepnotderp »

Hasz wrote: post #12
deepnotderp wrote: post #5

Earlier quoted context omitted.

Yes, although this can be an extra challenge in monolithic 3D because it often involves oxide layers and thin silicon * between transistor layers, which makes the heat conduction much worse. *due to violation of Fourier theory of heat.

How difficult would it be to replace current oxide layers with something like BeO?

I don't think anyone's tried but there can be all sorts of "fun" issues, e.g. directly putting many high-k oxides onto transistors results in fermi level pinning.

EDIT: I did look at this idea some time back and I believe AMD even has a patent on it (though I might be mistaken), it's possible, but might cause unexpected issues.

Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#14

Post by Hasz »

deepnotderp wrote: post #13
Hasz wrote: post #12

Earlier quoted context omitted.

How difficult would it be to replace current oxide layers with something like BeO?

I don't think anyone's tried but there can be all sorts of "fun" issues, e.g. directly putting many high-k oxides onto transistors results in fermi level pinning. EDIT: I did look at this idea some time back and I believe AMD even has a patent on it (though I might be mistaken), it's possible, but might cause unexpected issues.

Thanks -- any recommendations on a textbook for better understanding semiconductor physics?

I'm a physics major, but haven't gotten to do much semiconductor coursework yet.

Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#17

Post by deepnotderp »

Hasz wrote: post #14
deepnotderp wrote: post #13

Earlier quoted context omitted.

I don't think anyone's tried but there can be all sorts of "fun" issues, e.g. directly putting many high-k oxides onto transistors results in fermi level pinning. EDIT: I did look at this idea some time back and I believe AMD even has a patent on it (though I might be mistaken), it's possible, but might cause unexpected issues.

Thanks -- any recommendations on a textbook for better understanding semiconductor physics? I'm a physics major, but haven't gotten to do much semiconductor coursework yet.

So the issue is that stuff like this (e.g. Fermi level pinning induced by HfO2 directly on Si without a metal gate) tends to be industry "secret" stuff and tends to not be in textbooks. You'll usually catch this info from talking to process engineers and reading papers.

Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#18

Post by nhaehnle »

deepnotderp wrote: post #3
Invictus0 wrote: post #2

What exactly is the monolithic 3D integration process? In what way is this technology superior to the current state of the art?

Monolithic 3D is also sometimes called "sequential 3D". In essence, instead of current 3D integration which fabricates several 2D chips, then thins them, adds TSVs, aligns and then finally bonds them, Monolithic 3D makes 3D chips layer by layer. The advantages are that it can have extremely dense chip to chip connections, as much as ~10,000X as dense as TSVs (literally) and no ESD diode capacitance (can be as much as…

From what I understand, another disadvantage of monolithic 3D are the yield implications.

When you fabricate several 2D chips and then integrate them, it allows you to test those 2D chips for errors separately before the integration, which should give you better yields overall.

Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#19

Post by dev_dull »

mechagodzilla wrote: post #7

As a computer architect, I’m really curious what their practical capabilities will be for this process. There’s definitely a market for low volume / high performance chips if they can develop something interesting (ie mask costs similar to 90nm but performance closer to 7nm).

There’s security benefits (probably why it’s funded by darpa). It makes producing a lot of high performance chips economical outside of SE Asia.

Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones

#20

Post by antt »

Invictus0 wrote: post #2

What exactly is the monolithic 3D integration process? In what way is this technology superior to the current state of the art?

From the various articles in the thread it seems that these are single die computers, think something like bringing the cache on die from back in the day.
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