The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
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Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#2What exactly is the monolithic 3D integration process? In what way is this technology superior to the current state of the art?
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#3What exactly is the monolithic 3D integration process? In what way is this technology superior to the current state of the art?
Monolithic 3D is also sometimes called "sequential 3D". In essence, instead of current 3D integration which fabricates several 2D chips, then thins them, adds TSVs, aligns and then finally bonds them, Monolithic 3D makes 3D chips layer by layer.
The advantages are that it can have extremely dense chip to chip connections, as much as ~10,000X as dense as TSVs (literally) and no ESD diode capacitance (can be as much as ~50fF!!).
The disadvantages are that copper interconnects melt above ~400 degrees celsius, and we are around ~1200 degrees celsius to make transistors. There are a few ways around this but they usually result in crummier transistors.
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#4What exactly is the monolithic 3D integration process? In what way is this technology superior to the current state of the art?
Monolithic 3D is also sometimes called "sequential 3D". In essence, instead of current 3D integration which fabricates several 2D chips, then thins them, adds TSVs, aligns and then finally bonds them, Monolithic 3D makes 3D chips layer by layer. The advantages are that it can have extremely dense chip to chip connections, as much as ~10,000X as dense as TSVs (literally) and no ESD diode capacitance (can be as much as…
people mention terrible heat dissipation in 3D, do they allocate thermal vias between the layers?
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#5Earlier quoted context omitted.
Monolithic 3D is also sometimes called "sequential 3D". In essence, instead of current 3D integration which fabricates several 2D chips, then thins them, adds TSVs, aligns and then finally bonds them, Monolithic 3D makes 3D chips layer by layer. The advantages are that it can have extremely dense chip to chip connections, as much as ~10,000X as dense as TSVs (literally) and no ESD diode capacitance (can be as much as…
people mention terrible heat dissipation in 3D, do they allocate thermal vias between the layers?
Yes, although this can be an extra challenge in monolithic 3D because it often involves oxide layers and thin silicon * between transistor layers, which makes the heat conduction much worse.
*due to violation of Fourier theory of heat.
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#6[deleted]
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#7As a computer architect, I’m really curious what their practical capabilities will be for this process. There’s definitely a market for low volume / high performance chips if they can develop something interesting (ie mask costs similar to 90nm but performance closer to 7nm).
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#8What stops us from wrapping the circuits around the sides of the chip? Holding onto them? Or the fact that stacking gets you more layers than 2 1/2?
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#9There is a special IBM chip Fab in upstate New York that makes things for the NSA and DoD. They don't care if things are on a slightly older process.
See also, the DoD trusted foundry program
https://www.google.com/search?q=dod+trusted+foundry+program&...
Re: The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones
#10What stops us from wrapping the circuits around the sides of the chip? Holding onto them? Or the fact that stacking gets you more layers than 2 1/2?
Wrapping around sides isn't easy because chips are cut from a single large wafer pretty late in manufacturing. The sides aren't exposed until the end.
Besides, it won't help much. Usually when people want to shrink chips, it's often because shorter links. This means lower latency (ie faster) and lower heat loss. Wrapping or stacking doesn't help those.